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1.0 Product Description
1.1 Components of the Bt8230
Bt8230
ATM Segmentation and Reassembly Controller—SAR
N8230DS1F
ted into 52-byte ATM cells, not including the Header Error Control (HEC) byte.
(A blank HEC byte is added by the ATM physical interface block.) This task is
performed with the help of state tables in local RAM memory. Rate entries for
each segmentation connection allow the segmentation coprocessor to automati-
cally multiplex cells from a number of outgoing channels onto a single outgoing
link while preserving the bandwidth relations between the channels. The segmen-
tation coprocessor can also supply the Common Part Conversion Sublayer
(CPCS)-Protocol Data Unit (PDU) header, trailer, and pad fields as part of the
segmentation process.
1.1.3 Reassembly Coprocessor
The ATM physical block strips the HEC byte before passing the cell to the reas-
sembly coprocessor. The reassembly coprocessor then processes the 52-octet
cells. It controls the writing of the CPCS payload to host memory and performs
all necessary Segmentation and Reassembly (SAR) and CPCS checks.
The reassembly coprocessor uses a scatter method to write the payload portion
of the ATM cell to host memory. It maintains a free buffer queue and status queue
in local memory to control the scatter operation. The free buffer queue is updated
by the host processor to point to available cell buffers in host memory. The reas-
sembly coprocessor updates the status queue with information on how the cell
buffers are used. A hash table and a reassembly Virtual Circuit Channel (VCC)
table located in local memory operate the various CPCS connections and are
maintained by the reassembly coprocessor. The hash table allows the reassembly
coprocessor to quickly locate the appropriate reassembly VCC table based upon
the received VPI/VCI value in the ATM cell header, and permits the assignment
of any VPI/VCI value to a particular connection.
1.1.4 PCI Bus Interface
The PCI bus interface responds to read and write requests by the host CPU as a
PCI slave, allowing access to the chip resources by software on the host. The
Bt8230 is capable of acting as a DMA bus master on the PCI bus. As a result, the
PCI bus interface implements the full set of address, data, and control signals
required to drive the bus as a master. It also contains the logic required to support
arbitration for the PCI bus. This interface is PCI Version 2.0 compliant.
1.1.5 Local Memory Interface
The Bt8230 contains a memory controller that allows the device to access up to 8
Mbytes of static RAM memory. The memory controller also coordinates access to
the internal control and status registers by the host and local processors. Both zero
and single wait state access to SRAM are supported, which enables various price
and performance trade-offs to be made. In addition, SRAM devices organized
by_4, by_8, and by_16 may be used. Access to internal control and status regis-
ters follows the timing requirements of SRAM access, which simplifies system
implementations.