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參數(shù)資料
| 型號： | W28F641B |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 64MBIT (4MBIT 】 16) PAGE MODE DUAL WORK FLASH MEMORY |
| 中文描述： | 64兆比特（的4Mb】16）頁模式的雙工作閃存 |
| 文件頁數(shù)： | 10/31頁 |
| 文件大小： | 389K |
| 代理商： | W28F641B |
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W28F641B/T
Table 6. Command Definitions
(11)
FIRST BUS CYCLE
SECOND BUS CYCLE
COMMAND
BUS
CYCLES
REQ’D.
1
≥
2
≥
2
2
1
2
2
NOTE
Oper
(1)
Addr
(2)
Data
Oper
(1)
Addr
(2)
Data
(3)
Read Array
Read Identifier Codes/OTP
Read Query
Read Status Register
Clear Status Register
Block Erase
Full Chip Erase
4
4
5
Write
Write
Write
Write
Write
Write
Write
PA
PA
PA
PA
PA
BA
X
FFH
90H
98H
70H
50H
20H
30H
40H or
10H
E8H
Read
Read
Read
Write
Write
IA or OA ID or OD
QA
PA
BA
X
QD
SRD
D0H
D0H
5, 9
Program
2
5, 6
Write
WA
Write
WA
WD
Page Buffer Program
Block Erase and (Page Buffer)
Program Suspend
Block Erase and (Page Buffer)
Program Resume
Set Block Lock Bit
Clear Block Lock Bit
Set Block Lock-down Bit
OTP Program
Set Partition configuration
Register
≥
4
5, 7
Write
WA
Write
WA
N-1
1
8, 9
Write
PA
B0H
1
8, 9
Write
PA
D0H
2
2
2
2
Write
Write
Write
Write
BA
BA
BA
OA
60H
60H
60H
C0H
Write
Write
Write
Write
BA
BA
BA
OA
01H
D0H
2FH
OD
10
9
2
Write
PCRC
60H
Write
PCRC
04H
Notes:
1. Bus operations are defined in Table 5.
2. All address which is written at the first bus cycle should be the same as the address which is written at the second bus cycle.
X = Any valid address within the device.
PA = Address within the selected partition.
IA = Identifier codes address (See Table 3 and Table 4).
QA = Query codes address. Refer to Appendix for details.
BA = Address within the block being erased, set/cleared block lock bit or set block lock-down bit.
WA = Address of memory location for the Program command or the first address for the Page Buffer Program command.
OA = Address of OTP block to be read or programmed (See Figure 3).
PCRC = Partition configuration register code presented on the address A0
A15.
3. ID = Data read from identifier codes. (See Table 3 and Table 4).
QD = Data read from query database. Refer to Appendix for details.
SRD = Data read from status register. See Table 10 and Table 11 for a description of the status register bits.
WD = Data to be programmed at location WA. Data is latched on the rising edge of #WE or #CE (whichever goes high first)
during command write cycles.
OD = Data within OTP block. Data is latched on the rising edge of #WE or #CE (whichever goes high first) during command
write cycles.
N-1 = N is the number of the words to be loaded into a page buffer.
4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock
configuration code, partition configuration register code and the data within OTP block (See Table 3 and Table 4). The Read
Query command is available for reading CFI (Common Flash Interface) information.
5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block
can be erased or programmed when #RESET is V
IH
.
6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.
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