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參數資料
| 型號： | W28F641B |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 64MBIT (4MBIT 】 16) PAGE MODE DUAL WORK FLASH MEMORY |
| 中文描述： | 64兆比特（的4Mb】16）頁模式的雙工作閃存 |
| 文件頁數： | 19/31頁 |
| 文件大小： | 389K |
| 代理商： | W28F641B |
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W28F641B/T
Publication Release Date: March 27, 2003
DC Characteristics, continued
V
DD
= 2.7V
3.6V
PARAMETER
SYM.
TEST
CONDITIONS
Min.
Typ.
Max.
UNIT
Input Low Voltage (note 5)
V
IL
-0.4
0.4
V
Input High Voltage (note 5)
V
IH
2.4
V
DDQ
+0.4
V
Output Low Voltage (note 5)
V
OL
V
DD
= V
DD
Min., V
DDQ
=
V
DDQ
Min., I
OL
= 100
μ
A
0.2
V
Output High Voltage (note 5)
V
OH
V
DD
= V
DD
Min., V
DDQ
=
V
DDQ
Min., I
OH
= -100
μ
A
V
DDQ
-0.2
V
V
PP
Lockout during Normal Operations
(note 3, 5, 6)
V
PPLK
0.4
V
V
PP
during Block Erase, Full Chip
Erase, (Page Buffer) Program or OTP
Program Operations (note 6)
V
PPH1
1.65
3.0
3.6
V
V
PP
during Block Erase, (Page Buffer)
Program or OTP Program Operations
(note 6)
V
PPH2
11.7
12
12.3
V
V
DD
Lockout Voltage
V
LKO
1.5
V
Notes:
1. All currents are in RMS unless otherwise noted. Typical values are the reference values at V
DD
= 3.0V and T
A
= +25
°
C unless
V
DD
is specified.
2. I
CCWS
and I
CCES
are specified with the device de-selected. If read or (page buffer) program is executed while in block erase
suspend mode, the device's current draw is the sum of I
CCES
and I
CCR
or I
CCW
. If read is executed while in (page buffer)
program suspend mode, the device’s current draw is the sum of I
CCWS
and I
CCR
.
3. Block erases, full chip erase, (page buffer) program and OTP program are inhibited when V
PP
≤
V
PPLK
, and not guaranteed in
the range between V
PPLK
(max.) and V
PPH1
(min.), between V
PPH1
(max.) and V
PPH2
(min.) and above V
PPH2
(max.).
4. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle completion.
Standard address access timings (t
AVQV
) provide new data when address are changed.
5. Sampled, not 100% tested.
6. V
PP
is not used for power supply pin. With V
PP
≤
V
PPLK
, block erase, full chip erase, (page buffer) program and OTP program
cannot be executed and should not be attempted.
Applying 12V ±0.3V to V V
PP
provides fast erasing or fast programming mode. In this mode, V
PP
is power supply pin and
supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace widths and
layout considerations given to the V
DD
power bus.
Applying 12V ±0.3V to V
PP
during erase/program can only be done for a maximum of 1,000 cycles on each block. V
PP
may be
connected to 12V ±0.3V for a total of 80 hours maximum.
7. The operating current in dual work is the sum of the operating current (read, erase, program) in each plane.
- 19 -
Revision A3
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