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參數資料
| 型號： | W28F641B |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 64MBIT (4MBIT 】 16) PAGE MODE DUAL WORK FLASH MEMORY |
| 中文描述： | 64兆比特（的4Mb】16）頁模式的雙工作閃存 |
| 文件頁數： | 23/31頁 |
| 文件大小： | 389K |
| 代理商： | W28F641B |
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W28F641B/T
Publication Release Date: March 27, 2003
AC Characteristics - Write Operations
(1, 2)
V
DD
= 2.7V to 3.6V, T
A
= -40
°
C to +85
°
C
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Write Cycle Time
t
AVAV
80
nS
#RESET High Recovery to #WE(#CE) Going Low (note 3)
t
PHWL
(t
PHEL
)
150
nS
#CE(#WE) Setup to #WE(#CE) Going Low
t
ELWL
(t
WLEL
)
0
nS
#WE(#CE) Pulse Width (note 4)
t
WLWH
(t
ELEH
)
50
nS
Data Setup to #WE(#CE) Going High (note 8)
t
DVWH
(t
DVEH
)
40
nS
Address Setup to #WE(#CE) Going High (note 8)
t
AVWH
(t
AVEH
)
50
nS
#CE(#WE) Hold from #WE(#CE) High
t
WHEH
(t
EHWH
)
0
nS
Data Hold from #WE(#CE) High
t
WHDX
(t
EHDX
)
0
nS
Address Hold from #WE(#CE) High
t
WHAX
(t
EHAX
)
0
nS
#WE(#CE) Pulse Width High (note 5)
t
WHWL
(t
EHEL
)
30
nS
#WP High Setup to #WE(#CE) Going High (note 3)
t
SHWH
(t
SHEH
)
0
nS
V
PP
Setup to #WE(#CE) Going High (note 3)
t
VVWH
(t
VVEH
)
200
nS
Write Recovery before Read
t
WHGL
(t
EHGL
)
30
nS
#WP High Hold from Valid SRD (note 3,6)
t
QVSL
0
nS
V
PP
Hold from Valid SRD (note 3,6)
t
QVVL
0
nS
#WE(#CE) High to SR.7 Going "0" (note 3,7)
t
WHR0
(t
EHR0
)
t
AVQV
+50
nS
Notes:
1. The timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program and OTP
program operations are the same as during read-only operations. Refer to AC Characteristics for read-only operations.
2. A write operation can be initiated and terminated with either #CE or #WE.
3. Sampled, not 100% tested.
4. Write pulse width (t
WP
) is defined from the falling edge of #CE or #WE (whichever goes low last) to the rising edge of #CE or
#WE (whichever goes high first). Hence, t
WP
= t
WLWH
= t
ELEH
= t
WLEH
= t
ELWH
.
5. Write pulse width high (t
WPH
) is defined from the rising edge of #CE or #WE (whichever goes high first) to the falling edge of
#CE or #WE (whichever goes low last). Hence, t
WPH
= t
WHWL
= t
EHEL
= t
WHEL
= t
EHWL
.
6. V
PP
should be held at V
PP
= V
PPH1/2
until determination of block erase, (page buffer) program or OTP program success
(SR.1/3/4/5 = 0) and held at V
PP
= V
PPH1
until determination of full chip erase success (SR.1/3/5 = 0).
7. t
WHR0
(t
EHR0
) after the Read Query or Read Identifier Codes/OTP command = t
AVQV
+100 nS.
8. Refer to Table 6 for valid address and data for block erase, full chip erase, (page buffer) program, OTP program or lock bit
configuration.
- 23 -
Revision A3
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