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參數(shù)資料
型號： W28F641B
廠商： WINBOND ELECTRONICS CORP
英文描述： 64MBIT (4MBIT 】 16) PAGE MODE DUAL WORK FLASH MEMORY
中文描述： 64兆比特（的4Mb】16）頁模式的雙工作閃存
文件頁數(shù)： 20/31頁
文件大?。?/td> 389K
代理商： W28F641B
W28F641B/T
AC Characteristics - Read-only Operations(1)
V
DD
= 2.7V to 3.6V, T
A
= -40
°
C to +85
°
C
PARAMETER
SYM.
MIN.
MAX.
UNIT
Read Cycle Time
t
AVAV
80
nS
Address to Output Delay
t
AVQV
80
nS
#CE to Output Delay (note 3)
t
ELQV
80
nS
Page Address Access Time
t
APA
35
nS
#OE to Output Delay (note 3)
t
GLQV
20
nS
#RESET High to Output Delay
t
PHQV
150
nS
#CE or #OE to Output in High Z, whichever Occurs First (note 2)
t
EHQZ,
t
GHQZ,
20
nS
#CE to Output in Low Z (note 2)
t
ELQX
0
nS
#OE to Output in Low Z (note 2)
t
GLQX
0
nS
Output Hold from first Occurring Address, #CE or #OE Change
(note 2)
t
OH
0
nS
Address Setup to #CE, #OE, Going Low for Reading Status
Register (note 4,6)
t
AVEL,
t
AVGL
10
nS
Address Hold from #CE, #OE, Going Low for Reading Status
Register (note 5,6)
t
ELAX,
t
GLAX
30
nS
#CE, #OE Pulse Width High for Reading Status Register (note 6)
t
EHEL,
t
GHGL
30
nS
Notes:
1. See AC Input/Output Reference Waveform for timing measurements and maximum allowable input slew rate.
2. Sampled, not 100% tested.
3. #OE may be delayed up to t
ELQV
to t
GLQV
after the falling edge of #CE without impact to t
ELQV
.
4. Address setup time (t
AVEL
to t
AVGL
) is defined from the falling edge of #CE or #OE (whichever goes low last).
5. Address hold time (t
ELAX
to t
GLAX
) is defined from the falling edge of #CE or #OE (whichever goes low last).
6. Specifications t
AVEL
, t
AVGL
, t
ELAX
, t
GLAX
, and t
EHEL,
, t
GHGL
for read operations apply to only status register read operations.
- 20 -
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