
W39V040A
- 28 -
Timing Waveforms for LPC Interface Mode, continued
Chip Erase Timing Diagram
6th Start
Load Address "5555" in 8 Clocks
1 Clock
1 Clock
TAR
Sync
Internal
TAR
1 Clock
011Xb
0000b
XXXXb
XXXXb
XXXXb
XXXXb
X101b
Load Data "10"
0001b
Write the 6th command to the device in LPC mode.
0101b
0101b
0101b
0000b
1111b
Tri-State
0000b
Data
Address
LAD[3:0]
1st Start
CLK
TAR
Start next
011Xb
0000b
XXXXb
XXXXb
XXXXb
XXXXb
X101b
0101b
0101b
0101b
1010b
1010b
LAD[3:0]
CLK
LAD[3:0]
CLK
LAD[3:0]
CLK
Address
Sync
TAR
Data
Load Address "5555" in 8 Clocks
1 Clock
1 Clock
1 Clock
2 Clocks
1 Clock
Load Data "AA"
in 2 Clocks
Write the 1st command to the device in LPC mode.
2nd Start
Load Address "2AAA" in 8 Clocks
1 Clock
1 Clock
TAR
Start next
1 Clock
2 Clocks
1 Clock
011Xb
0000b
XXXXb
XXXXb
XXXXb
XXXXb
X010b
1010b
1010b
1010b
Load Data "55"
0101b
0101b
Write the 2nd command to the device in LPC mode.
3rd Start
Load Address "5555" in 8 Clocks
1 Clock
1 Clock
TAR
Start next
1 Clock
2 Clocks
1 Clock
011Xb
0000b
XXXXb
XXXXb
XXXXb
XXXXb
X101b
0101b
0101b
0101b
Load Data "80"
1000b
0000b
Write the 3rd command to the device in LPC mode.
Address
Address
Sync
TAR
Data
Sync
TAR
Data
1111b
Tri-State
0000b
1111b
Tri-State
0000b
1111b
Tri-State
0000b
4th Start
Load Address "5555" in 8 Clocks
1 Clock
1 Clock
TAR
Start next
1 Clock
2 Clocks
1 Clock
011Xb
0000b
XXXXb
XXXXb
XXXXb
XXXXb
X101b
0101b
0101b
0101b
Load Data "AA"
in 2 Clocks
1010b
1010b
Write the 4th command to the device in LPC mode.
5th Start
Load Address "2AAA" in 8 Clocks
1 Clock
1 Clock
TAR
Start next
command
1 Clock
2 Clocks
1 Clock
011Xb
0000b
XXXXb
XXXXb
XXXXb
XXXXb
X010b
1010b
1010b
1010b
Load Data "55"
0101b
0101b
Write the 5th command to the device in LPC mode.
Address
Address
Sync
TAR
Data
Sync
TAR
Data
1111b
Tri-State
0000b
1111b
Tri-State
0000b
LAD[3:0]
CLK
LAD[3:0]
CLK
2 Clocks
Memory
Cycle
Memory
Memory
Memory
Cycle
Memory
Memory
Cycle
Internal
#LFRAM
#RESET
#LFRAM
#RESET
#LFRAM
#RESET
#LFRAM
#RESET
#LFRAM
#RESET
#LFRAM
#RESET