
Preliminary W79E225A/227A Data Sheet
Publication Release Date: December 14, 2007
- 35 -
Revision A2.0
P4.1 BASE ADDRESS HIGH BYTE REGISTER
Bit:
7
6
5
4
3
2
1
0
A15
A14
A13
A12
A11
A10
A9
A8
Mnemonic: P41AH
Address: 97h
SERIAL PORT CONTROL
Bit:
7
6
5
4
3
2
1
0
SM0/FE
SM1
SM2
REN
TB8
RB8
TI
RI
Mnemonic: SCON
Address: 98h
BIT
NAME
FUNCTION
7
SM0/FE
Serial Port mode select bit 0 or Framing Error Flag: This bit is controlled by the
SMOD0 bit in the PCON register.
(SM0) See table below.
(FE) This bit indicates an invalid stop bit. It must be manually cleared by software.
Serial Port mode select bit 1. See table below.
Serial Port Clock or Multi-Processor Communication.
(Mode 0) This bit controls the serial port clock. If set to zero, the serial port runs at a
divide-by-12 clock of the oscillator. This is compatible with the standard 8051/52. If
set to one, the serial clock is a divide-by-4 clock of the oscillator.
(Mode 1) If SM2 is set to one, RI is not activated if a valid stop bit is not received.
(Modes 2 / 3) This bit enables multi-processor communication. If SM2 is set to one,
RI is not activated if RB8, the ninth data bit, is zero.
Receive enable:
1: Enable serial reception.
0: Disable serial reception.
(Modes 2 / 3) This is the 9th bit to transmit. This bit is set by software.
(Mode 0) No function.
(Mode 1) If SM2 = 0, RB8 is the stop bit that was received.
(Modes 2 / 3) This is the 9th bit that was received.
Transmit interrupt flag: This flag is set by the hardware at the end of the 8th bit in
mode 0 or at the beginning of the stop bit in the other modes during serial
transmission. This bit must be cleared by software.
Receive interrupt flag: This flag is set by the hardware at the end of the 8th bit in
mode 0 or halfway through the stop bits in the other modes during serial reception.
However, SM2 can restrict this behavior. This bit can only be cleared by software.
6
SM1
5
SM2
4
REN
3
TB8
2
RB8
1
TI
0
RI
SM1, SM0: Mode Select bits:
SM0
SM1
MODE
DESCRIPTION
LENGTH
BAUD RATE
0
0
0
Synchronous
8
Tclk divided by 4 or 12
0
1
1
Asynchronous
10
Variable
1
0
2
Asynchronous
11
Tclk divided by 32 or 64
1
1
3
Asynchronous
11
Variable