- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄363901 > W79E804ASG (WINBOND ELECTRONICS CORP) 8-BIT MICROCONTROLLER PDF資料下載
參數(shù)資料
| 型號(hào)： | W79E804ASG |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, SOP-20 |
| 文件頁(yè)數(shù)： | 60/115頁(yè) |
| 文件大小： | 1456K |
| 代理商： | W79E804ASG |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)當(dāng)前第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)
W79E804A/803A/802A
- 60 -
12. INTERRUPTS
The W79E804 series have four priority level interrupts structure with 12 interrupt sources. Each of the
interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the
interrupts can be globally enabled or disabled.
12.1 Interrupt Sources
The External Interrupts
INT0
and
INT1
can be either edge triggered or level triggered, depending on
bits IT0 and IT1. The bits IE0 and IE1 in the TCON register are the flags which are checked to
generate the interrupt. In the edge triggered mode, the INTx inputs are sampled in every machine
cycle. If the sample is high in one cycle and low in the next, then a high to low transition is detected
and the interrupts request flag IEx in TCON is set. The flag bit requests the interrupt. Since the
external interrupts are sampled every machine cycle, they have to be held high or low for at least one
complete machine cycle. The IEx flag is automatically cleared when the service routine is called. If the
level triggered mode is selected, then the requesting source has to hold the pin low till the interrupt is
serviced. The IEx flag will not be cleared by the hardware on entering the service routine. If the
interrupt continues to be held low even after the service routine is completed, then the processor may
acknowledge another interrupt request from the same source.
The Timer 0 and 1 Interrupts are generated by the TF0 and TF1 flags. These flags are set by the
overflow in the Timer 0 and Timer 1. The TF0 and TF1 flags are automatically cleared by the hardware
when the timer interrupt is serviced. The Watchdog timer can be used as a system monitor or a simple
timer. In either case, when the time-out count is reached, the Watchdog Timer interrupt flag WDIF
(WDCON.3) is set. If the interrupt is enabled by the enable bit EIE.4, then an interrupt will occur.
The Serial block can generate interrupt on reception or transmission. There are two interrupt sources
from the Serial block, which are obtained by the RI and TI bits in the SCON SFR. These bits are not
automatically cleared by the hardware, and the user will have to clear these bits by software.
All the bits that generate interrupts can be set or reset by software, and thereby software initiated
interrupts can be generated. Each of the individual interrupts can be enabled or disabled by setting or
clearing a bit in the IE SFR. IE also has a global enable/disable bit EA, which can be cleared to
disable all interrupts.
The two comparators can generate interrupt after comparator output has toggle occurs by CMF1 and
CMF2. These bits are not automatically cleared by the hardware, and the user will have to clear these
bits using software.
The I2C function can generate interrupt, if EI2C and EA bits are enabled, when SI Flag is set due to a
new I2C status code is generated, SI flag is generated by hardware and must be cleared by software.
The PWM function can generate interrupt by BKF flag, after external brake pin has brake occurred.
This bit will be cleared by software.
The interrupt flags are sampled every machine cycle. In the same machine cycle, the sampled
interrupts are polled and their priority is resolved. If certain conditions are met then the hardware will
execute an internally generated LCALL instruction which will vector the process to the appropriate
interrupt vector address. The conditions for generating the LCALL are;
1. An interrupt of equal or higher priority is not currently being serviced.
2. The current polling cycle is the last machine cycle of the instruction currently being execute.
3. The current instruction does not involve a write to IE, EIE, IP0, IP0H, IP1 or IPH1 registers and is
not a RETI.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W80NF06 | N-CHANNEL 60V - 0.0065OHM - 80A TO-220/D2PAK/TO-247 STripFET II POWER MOSFET |
| W81181AD | USB HUB CONTROLLER |
| W81181D | USB HUB CONTROLLER |
| W81282F-05 | USB Keyboard Controller with 4 Ports Hub |
| W81386-DG | Winbond USB Interface MS/SD/MMC Reader |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W79E8213 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:W79E8213中文資料 |
| W79E8213_W79E8213R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Table of contents- |
| W79E8213AKG | 制造商:Nuvoton Technology Corp 功能描述:IC MCU 8BIT 4K FLASH 20DIP |
| W79E8213ASG | 制造商:Nuvoton Technology Corp 功能描述:IC MCU 8BIT 4K FLASH 20SOP |
| W79E8213RAKG | 制造商:Nuvoton Technology Corp 功能描述:IC MCU 8BIT 4K FLASH 20DIP |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。