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參數(shù)資料
| 型號(hào)： | W79E804ASG |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, SOP-20 |
| 文件頁(yè)數(shù)： | 96/115頁(yè) |
| 文件大小： | 1456K |
| 代理商： | W79E804ASG |
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W79E804A/803A/802A
- 96 -
24.2 The I2C Control Registers:
The I2C has 1 control register (I2CON) to control the transmit/receive flow, 1 data register (I2DAT) to
buffer the Tx/Rx data, 1 status register (I2STATUS) to catch the state of Tx/Rx, recognizable slave
address register for slave mode use and 1 clock rate control block for master mode to generate the
variable baud rate.
24.2.1 The Address Registers, I2ADDR
I2C port is equipped with one slave address register. The contents of the register are irrelevant when
I2C is in master mode. In the slave mode, the seven most significant bits must be loaded with the
MCU’s own slave address. The I2C hardware will react if the contents of I2ADDR are matched with
the received slave address.
The I2C ports support the “General Call” function. If the GC bit is set the I2C port1 hardware will
respond to General Call address (00H). Clear GC bit to disable general call function.
When GC bit is set, the I2C is in Slave mode, it can be received the general call address by 00H
after Master send general call address to I2C bus, then it will follow status of GC mode. If it is
in Master mode, the AA bit must be cleared when it will send general call address of 00H to I2C
bus.
24.2.2 The Data Register, I2DAT
This register contains a byte of serial data to be transmitted or a byte which has just been received.
The CPU can read from or write to this 8-bit directly addressable SFR while it is not in the process of
shifting a byte. This occurs when SIO is in a defined state and the serial interrupt flag (SI) is set. Data
in I2DAT remains stable as long as SI bit is set. While data is being shifted out, data on the bus is
simultaneously being shifted in; I2DAT always contains the last data byte present on the bus. Thus, in
the event of arbitration lost, the transition from master transmitter to slave receiver is made with the
correct data in I2DAT.
I2DAT and the acknowledge bit form a 9-bit shift register, the acknowledge bit is controlled by the SIO
hardware and cannot be accessed by the CPU. Serial data is shifted through the acknowledge bit into
I2DAT on the rising edges of serial clock pulses on the SCL line. When a byte has been shifted into
I2DAT, the serial data is available in I2DAT, and the acknowledge bit (ACK or NACK) is returned by
the control logic during the ninth clock pulse. Serial data is shifted out from I2DAT on the falling edges
of SCL clock pulses, and is shifted into I2DAT on the rising edges of SCL clock pulses.
I2DAT.7 I2DAT.6 I2DAT.5 I2DAT.4 I2DAT.3 I2DAT.2 I2DAT.1 I2DAT.0
shifting direction
I2C Data Register:
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