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參數資料
| 型號： | W79E804ASG |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | 0.300 INCH, ROHS COMPLIANT, SOP-20 |
| 文件頁數： | 80/115頁 |
| 文件大小： | 1456K |
| 代理商： | W79E804ASG |
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W79E804A/803A/802A
- 80 -
The Master processor can selectively communicate with groups of slaves by using the Given Address.
All the slaves can be addressed together using the Broadcast Address. The addresses for each slave
are defined by the SADDR and SADEN SFRs. The slave address is an 8-bit value specified in the
SADDR SFR. The SADEN SFR is actually a mask for the byte value in SADDR. If a bit position in
SADEN is 0, then the corresponding bit position in SADDR is don't care. Only those bit positions in
SADDR whose corresponding bits in SADEN are 1 are used to obtain the Given Address. This gives
the user flexibility to address multiple slaves without changing the slave address in SADDR.
The following example shows how the user can define the Given Address to address different slaves.
Slave 1:
SADDR 1010 0100
SADEN 1111 1010
Given 1010 0x0x
Slave 2:
SADDR 1010 0111
SADEN 1111 1001
Given 1010 0xx1
The Given address for slave 1 and 2 differ in the LSB. For slave 1, it is a don't care, while for slave 2 it
is 1. Thus to communicate only with slave 1, the master must send an address with LSB = 0 (1010
0000). Similarly the bit 1 position is 0 for slave 1 and don't care for slave 2. Hence to communicate
only with slave 2 the master has to transmit an address with bit 1 = 1 (1010 0011). If the master
wishes to communicate with both slaves simultaneously, then the address must have bit 0 = 1 and bit
1 = 0. The bit 3 position is don't care for both the slaves. This allows two different addresses to select
both slaves (1010 0001 and 1010 0101).
The master can communicate with all the slaves simultaneously with the Broadcast Address. This
address is formed from the logical OR of the SADDR and SADEN SFRs. The zeros in the result are
defined as don't cares. In most cases the Broadcast Address is FFh. In the previous case, the
Broadcast Address is (1111111x) for slave 1 and (11111111) for slave 2.
The SADDR and SADEN SFRs are located at address A9h and B9h respectively. On reset, these two
SFRs are initialized to 00h. This results in Given Address and Broadcast Address being set as xxxx
xxxx (i.e. all bits don't care). This effectively removes the multiprocessor communications feature,
since any selectivity is disabled.
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