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參數資料
型號： W79E804ASG
廠商： WINBOND ELECTRONICS CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT MICROCONTROLLER
中文描述： 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDSO20
封裝： 0.300 INCH, ROHS COMPLIANT, SOP-20
文件頁數： 97/115頁
文件大?。?/td> 1456K
代理商： W79E804ASG
W79E804A/803A/802A
Publication Release Date: July 16, 2007
- 97 -
Revision A2
24.2.3 The Control Register, I2CON
The CPU can read from and write to this 8-bit, directly addressable SFR. Two bits are affected by
hardware: the SI bit is set when the I2C hardware requests a serial interrupt, and the STO bit is
cleared when a STOP condition is present on the bus. The STO bit is also cleared when ENS = "0".
ENSI
Set to enable I2C serial function block. When ENS=1 the I2C serial function enables. The
port latches of SDA1 and SCL1 must be set to logic high.
STA
I2C START Flag. Setting STA to logic 1 to enter master mode, the I2C hardware sends a
START or repeat START condition to bus when the bus is free.
STO
I2C STOP Flag. In master mode, setting STO to transmit a STOP condition to bus then
I2C hardware will check the bus condition if a STOP condition is detected this flag will be
cleared by hardware automatically. In a slave mode, setting STO resets I2C hardware to
the defined “not addressed” slave mode. This means it is NO LONGER in the slave
receiver mode to receive data from the master transmit device.
SI
I2C Port 1 Interrupt Flag. When a new SIO state is present in the S1STA register, the SI
flag is set by hardware, and if the EA and EI2C1 bits are both set, the I2C1 interrupt is
requested. SI must be cleared by software.
AA
Assert Acknowledge control bit. When AA=1 prior to address or data received, an
acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on
the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The
receiver devices are acknowledging the data sent by transmitter. When AA=0 prior to
address or data received, a Not acknowledged (high level to SDA) will be returned during
the acknowledge clock pulse on the SCL line.
24.2.4 The Status Register, I2STATUS
I2STATUS is an 8-bit read-only register. The three least significant bits are always 0. The five most
significant bits contain the status code. There are 23 possible status codes. When I2STATUS contains
F8H, no serial interrupt is requested. All other I2STATUS values correspond to defined SIO states.
When each of these states is entered, a status interrupt is requested (SI = 1). A valid status code is
present in I2STATUS one machine cycle after SI is set by hardware and is still present one machine
cycle after SI has been reset by software.
24.2.5 The I2C Clock Baud Rate Bits, I2CLK
The data baud rate of I2C is determines by I2CLK register when SIO is in a master mode. It is not
important when SIO is in a slave mode. In the slave modes, SIO will automatically synchronize with
any clock frequency up to 400 KHz from master I2C device.
The data baud rate of I2C setting is Data Baud Rate of I2C = Fcpu / (I2CLK+1). The Fcpu=Fosc/4. If
Fosc = 16MHz, the I2CLK = 40(28H), so data baud rate of I2C = 16MHz/(4X (40 +1)) =
97.56Kbits/sec. The block diagram is as below figure.
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