
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
Publication Release Date: Jan 1999
- 11 - Revision 0.32
1.2 W83629D PIN DESCRIPTION
1.2.1 Control Logic and Handshaking Signals
SYMBOL
HS[2:0]
PIN
17-15
I/O
FUNCTION
I/O12
Handshaking Signals.
HS[2:0] connected to W83628F for PCI
to ISA SET handshaking signals.
NO GO.
This signal indicates which master initiated the current
transaction and also indicates whether or not the current bus
cycle is targeted for the ISA bus. This signal is a point-to-point
connection between PCI HOST Bridge and W83628F.
NOGO
40
INt
PCICLK
44
INt
PCI Bus System Clock
. PCICLK provides timing for all
transactions on the PCI bus. All other PCI signals are sampled
on the rising edge of PCICLK, and all timing parameters are
defined with respect to this edge.
PCIRST#
47
INt
PCI Reset.
W83628F receives PCIRST# as a reset from the PCI
Bus.
1.2.2 PC/PCI Interface
SYMBOL
ISAREQ#
PIN
41
I/O
FUNCTION
OUT24t
ISA Bus Request.
This signal is a point-to-point signal between
W83629D and a PCI HOST arbiter . The W83629D asserts this
signal according to the PC/PCI protocol.
ISA Bus Grant.
This signal is a point-to-point signal between
W83629D and a PCI HOST Bridge
s
secondary bus
PCPCIGNT# signal. W83629D asserts this signal according to
the PC/PCI protocol.
DMA Request.
The DREQ signal indicates that either a slave
DMA device is requesting DMA services, or an ISA bus master is
requesting use of the ISA bus.
ISAGNT#
42
INt
DRQ
[7:5,3:0]
35,33
31,28
26,23
21
34,32
30,27
24,22
20
19
INt
DACK
[7:5,3:0]#
OUT24t
DMA Acknowledge.
The DACK# signal indicates that either a
DMA channel or an ISA bus master has been granted the ISA
bus.
TC
OUT24t
Terminal Count.
The W83628F asserts TC to DMA slaves as a
terminal count indicator.