
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
Publication Release Date: Jan 1999
- 15 - Revision 0.32
Bit 6
66 MHz/ 33 MHz(Only support 33 MHz).
Hardwired to zero.
User Defineable Features(Not supported).
Hardwired to zero.
Reserved.
Reserved and will returns zero when reading this register.
Bit 5
Bit 4
:
0
2.5 REVID-REVISION IDENTIFICATION REGISTER
Address Offset:
08h
Default Value:
See lastest stepping information
Attribute:
Read Only
This register shows status information for PCI bus related events.
Bit 7
:
0
Revision Identification Number.
2.6 CCODE-CALSS CODE REGISTER
Address Offset:
Default Value:
Attribute:
The class code register is a read-only register and used to identify the ISA bridge.
Bit 23:16
Base Class Code.
06h = Bus Bridge
Bit 15:8
Sub-Class Code.
01h = PCI to ISA Bridge
Bit 7:0
Programming Interface.
00h
09-0Bh
060100h
Read Only
2.7 HEADT-HEAD TYPE REGISTER
Address Offset:
0Eh
Default Value:
00h
Attribute:
Read Only
The register is a read-only register and used to indicate that the ISA bridge configuration space
adheres to PCI local bus specification. It also indicates that ISA bridge is not a multifunction device.
Bit 7
Multifunction Indicator.
0 = Not a multifunction device.
Bit 6:0
Layout Code.
00h = PCI layout type.