- 您現在的位置：買賣IC網 > PDF目錄363902 > W83628F (WINBOND ELECTRONICS CORP) PCI TO ISA BRIDGE SET PDF資料下載
參數資料
| 型號： | W83628F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI TO ISA BRIDGE SET |
| 中文描述： | ISA BUS CONTROLLER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數： | 6/27頁 |
| 文件大?。?/td> | 271K |
| 代理商： | W83628F |
第1頁第2頁第3頁第4頁第5頁當前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
Publication Release Date: Jan 1999
- 6 -
Revision 0.32
1. PIN DESCRIPTION
Note: Please refer to Section 13.2 DC CHARACTERISTICS for details.
I/O12t
- TTL level bi-directional pin with 12 mA source-sink capability
I/O24t
- TTL level bi-directional pin with 24 mA source-sink capability
I/O12tp3
- 3.3V TTL level bi-directional pin with 12 mA source-sink capability
I/O24tp3
- 3.3V TTL level bi-directional pin with 24 mA source-sink capability
I/OD12t
- TTL level bi-directional pin open drain output with 12 mA sink capability
I/O24t
- TTL level bi-directional pin with 24 mA source-sink capability
OUT12t
- TTL level output pin with 12 mA source-sink capability
OUT24t
- TTL level output pin with 24 mA source-sink capability
OUT12tp3
- 3.3V TTL level output pin with 12 mA source-sink capability
OUT24tp3
- 3.3V TTL level output pin with 24 mA source-sink capability
OD12
- Open-drain output pin with 12 mA sink capability
OD24
- Open-drain output pin with 24 mA sink capability
INcs
- CMOS level Schmitt-trigger input pin
INt
- TTL level input pin
INtd
- TTL level input pin with internal pull down resistor
INts
- TTL level Schmitt-trigger input pin
INtsp3
- 3.3V TTL level Schmitt-trigger input pin
1.1 W83628F PIN DESCRIPTION
1.1.1
PCI Interface
SYMBOL
AD[31:0]
PIN
19-26
30-37
52-59
61-63
66-70
28,45
51,60
I/O
FUNCTION
I/O24tp3
PCI Bus Address and Data Signals.
The standard PCI address
and data lines. Address is driven with FRAME# assertion, data is
driven or received in following clocks.
C/BE[3:0]#
I/O24tp3
PCI Bus Command and Byte Enables.
During the address
phase of a transaction C/BE[3:0]# define the bus command.
During the data phase C/BE[3:0]# are used as Byte Enables.
PCI Bus System Clock
. PCICLK provides timing for all
transactions on the PCI bus. All other PCI signals are sampled
on the rising edge of PCICLK, and all timing parameters are
defined with respect to this edge.
PCI Bus System Clock DPLL Output.
The PCLK_OUT can
reduce the PCICLK Loading and it produced from internal DPLL.
PCICLK
47
INt
PCLK_OUT
48
OUT
12t
相關PDF資料 |
PDF描述 |
|---|---|
| W83637HF | LPC I/O |
| W83637HF-AW | LPC I/O |
| W83697HF | WINBOND I/O |
| W83697 | WINBOND I/O |
| W83697F | WINBOND I/O |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W83629AG | 制造商:Nuvoton Technology Corp 功能描述:PCI to ISA Bus Conversion 48-Pin LQFP |
| W83629D | 制造商:WINBOND 制造商全稱:Winbond 功能描述:PCI TO ISA BRIDGE SET |
| W83637HF | 制造商:WINBOND 制造商全稱:Winbond 功能描述:LPC I/O |
| W83637HF_06 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:LPC I/O |
| W83637HF-AW | 制造商:WINBOND 制造商全稱:Winbond 功能描述:LPC I/O |
發布緊急采購，3分鐘左右您將得到回復。