
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
Publication Release Date: Jan 1999
- 19 - Revision 0.32
2.16 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 5 MASK CONTROL
REGISTER
Address Offset:
5Dh
Default Value:
00h
Attribute:
Read/Write
This register is used to mask address bits(A7~A0) for fast address decoder # 5, if the corresponding
bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the faster address
decoder # 5.
2.17 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 6 MASK CONTROL
REGISTER
Address Offset:
5Eh
Default Value:
00h
Attribute:
Read/Write
This register is used to mask address bits(A7~A0) for fast address decoder # 6, if the corresponding
bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the faster address
decoder # 6.
2.18 WISA_FAD0MC-ISA BRIDGE FAST DECODERS # 7 MASK CONTROL
REGISTER
Address Offset:
5Fh
Default Value:
00h
Attribute:
Read/Write
This register is used to mask address bits(A7~A0) for fast address decoder # 7, if the corresponding
bit of this register is set to a 1, the corresponding address bit(A7~A0) is ignore by the faster address
decoder # 7.
2.19 WISA_FADCB0-ISA BRIDGE FAST DECODERS # 0 BASE ADDRESS
REGISTER
Address Offset:
60-61h**
Default Value:
0000h
Attribute:
Read/Write
This register contains the base address for fast address decoder # 0.A
**Note: 60h is lower byte and 61h is upper byte.