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參數資料
| 型號： | W83628F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI TO ISA BRIDGE SET |
| 中文描述： | ISA BUS CONTROLLER, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數： | 9/27頁 |
| 文件大小： | 271K |
| 代理商： | W83628F |
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PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
Publication Release Date: Jan 1999
- 9 -
Revision 0.32
1.1.3 ISA Interface, continued
SYMBOL
MEMR#
PIN
6
I/O
FUNCTION
I/O24t
Memory Read.
MEMR# asserted indicates the current ISA bus
cycle is a memory read.
Memory Write.
MEMW# asserted indicates the current ISA bus
cycle is a memory write.
MASTER#.
This signal is used with a DREQ line by an ISA
master to gain control of the ISA Bus.
Unlatched Address.
The LA[23:17] address lines are bi-
directional. These address lines allow accesses to physical
memory on the ISA Bus up to 16 Mbytes. LA[23:17] are outputs
when the W83628F owns the ISA Bus.
ROMCS# ,this pin weak pulled-down during PCIRST is
asserted, and apply a pull-up resistor (4.7 Kohm) to this pin
enable positive decoder of BIOS address range (depend on
Configure register 70 , bit 3,2). When BIOS assress range is
enabled , the PIN is BIOS ROM CS# output.
Refresh.
REFRESH# asserted indicates that a refresh cycle is in
progress, or that an ISA master is requesting W83628F to
generate a refresh cycle. Upon PCIRST#, this signal is tri-stated.
Zero Wait States.
An ISA slave asserts ZEROWS# after its
address and command signals have been decoded to indicate
that the current cycle can be executed as an ISA zero wait state
cycle. ZEROWS# has no effect during 16-bit I/O cycles.
Standard Memory Read.
SMEMR# asserted indicates the
current ISA bus cycle is a memory read cycle to an address
below 1 Mbyte.
Standard Memory Write.
SMEMW# asserted indicates the
current ISA bus cycle is a memory write cycle to an address
below 1 Mbyte.
Bus Address Latch Enable.
BALE is an active high signal
asserted by the W83628F to indicate that the address (SA[19:0],
LA[23:17]) and SBHE# signal lines are valid.
The LA[23:17] address lines are latched on the trailing edge of
BALE. BALE remains asserted throughout DMA and ISA master
cycles. BALE is driven low upon PCIRST#.
Memory Chip Select 16.
MEMCS16# asserted indicates that the
memory slave supports 16-bit accesses.
MEMW#
7
I/O24t
MASTER#
17
INt
LA[23:17]
5-2
127-
125
I/O24t
ROMCS#
73
I/O12
REFRESH#
75
I/O24t
ZEROWS#
106
INt
SMEMR#
117
OUT24t
SMEMW#
119
OUT24t
BALE
122
OUT24t
MEMCS16#
123
OD24
1.1.4 Power Signals
SYMBOL
VCC
3VCC
PIN
I/O
PWR
PWR
FUNCTION
1, 82, 102, 115
27, 46, 64
5V Supply.
3.3V Supply.
相關PDF資料 |
PDF描述 |
|---|---|
| W83637HF | LPC I/O |
| W83637HF-AW | LPC I/O |
| W83697HF | WINBOND I/O |
| W83697 | WINBOND I/O |
| W83697F | WINBOND I/O |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W83629AG | 制造商:Nuvoton Technology Corp 功能描述:PCI to ISA Bus Conversion 48-Pin LQFP |
| W83629D | 制造商:WINBOND 制造商全稱:Winbond 功能描述:PCI TO ISA BRIDGE SET |
| W83637HF | 制造商:WINBOND 制造商全稱:Winbond 功能描述:LPC I/O |
| W83637HF_06 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:LPC I/O |
| W83637HF-AW | 制造商:WINBOND 制造商全稱:Winbond 功能描述:LPC I/O |
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