
W83637HF
Publication Release Date: June 25, 2003
- 82 -
Revision 1.3
7.2 Register File
Complete register file table
Bit Number
Register file
Abbr.
7
6
5
4
3
2
1
0
Base + 0
BDLAB = 0
Receiver Buffer
Register (Read
only)
RBR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Base + 0
BDLAB = 0
Transmitter Buffer
Register (Write
only)
TBR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Interrupt Enable
Register
SCC8
SCC4
SCC8_IO
(note)
SCC4_IO
(note)
ESCPTI
(note)
ESCSRI
(note)
ETBREI
(note)
ERDRI
(note)
Base + 1
BDLAB = 0
default
IER
x
x
0
0
0
0
0
0
Base + 2
BDLAB = 0
Interrupt Status
Register (Read
only)
ISR
FIFO
enabled
FIFO
enabled
SCPSNT
SCPTI
(note)
INTS2
(note)
INTS1
(note)
INTS0
(note)
Interrupt
pending
Smart Card FIFO
control Register
(Write only)
RxTL1
(note)
RxTL0
(note)
Reserved Reserved Reserved
TxFRST
(note)
RxFRST
(note)
Enable
FIFO
Base + 2
BDLAB = 0
default
SCFR
0
0
x
x
x
0
0
0
Smart Card
Control
Register
BDLAB
(note)
Reserved Reserved
EPE
(note)
PBE
(note)
Reserved Reserved SC_SEL
Base + 3
default
SCCR
0
x
x
0
0
x
x
0
Clock Base
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Base + 4
default
CBR
0
0
0
0
1
1
0
0
Base + 5
Smart Card
Status
Register (Read
only)
SCSR
RxFEI
(note)
TSRE
(note)
TBRE
(note)
SBD
(note)
NSER
(note)
PBER
(note)
OER
(note)
RDR
(note)
Guard Time
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Base + 6
default
GTR
0
0
0
0
0
0
0
1
Extended Control
Register
Cold
reset
Reserved
SCKFS1
(note)
SCKFS0
(note)
CLKSTPL
(note)
CLKSTP
(note)
SCIODIR
(note)
Warm
reset
Base + 7
default
ECR
0
x
0
1
0
0
1
0
Baud rate divisor
Latch Lower byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Base + 0
BDLAB = 1
default
BLL
0
0
0
1
1
1
1
1
Baud rate divisor
Latch Higher byte
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Base + 1
BDLAB = 1
default
BLH
0
0
0
0
0
0
0
0
Base + 2
BDLAB = 1
Smart Card ID
number (Read
only)
0
1
1
1
0
0
0
0