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參數資料
| 型號： | W83637HF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | LPC I/O |
| 中文描述： | LPC的I / O |
| 文件頁數： | 99/149頁 |
| 文件大小： | 936K |
| 代理商： | W83637HF |
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W83637HF
Publication Release Date: June 25, 2003
- 94 -
Revision 1.3
7.3 Smart Card ID Number (base address + 2 when BDLAB = 1, fixed at 70h)
This register contains a specific value of 70h for driver to identify Smart Card interface.
7.4 Functional Description
The following description uses abbreviations to refer to control/status registers and their contents of
Smart Card interface as seen in section 2.2. Also, PnP resources of Smart Card interface are
assumed to have been programmed and allocated appropriately by system BIOS.
7.5 Initialization
User needs to program control registers so that ATR (Answer To Reset) data streams can be properly
decoded after card insertion. Initialization settings include the following steps where sequential order
is irrelevant.
1. BLH, BLL and CBR are written with 00h, 1Fh and 0Ch respectively to comply with default
transmission factors Fd and Dd which are 372 and 1 as specified in ISO/IEC 7816-3.
2. GTR is programmed with 01h for one stop bit.
3. Set SCFR bit 1 to "1" to enable FIFO.
4. PBE needs to be "1" for parity bit enable but EPE is optional.
5. Set SDIODIR to "1" to put SDIO in reception mode.
6. Set SCKFS1 and SCKFS0 to "01" to select 3 MHz for SCCLK.
Most default values of above control bits are designed as specified in initialization step but it is
recommended that user performs all the initialization sequence to avoid any ambiguity.
The relationship between transmission factors and settings of BLH, BLL and CBR is best described in
the following example.
f
1
D
F
etu
1
×
=
(f means SCCLK frequency)
Therefore,
(
)
12
31
CBR
BLL
,
BLH
1
372
Dd
Fd
×
=
×
=
=
7.6 Activation
Card insertion pulls up SCPSNT (assuming SCPSNT is active high with CRF0 bit 0 SCPSNT_POL = 0)
and in consequence SCPWR# is pulled down to activate power MOS to supply power to card slot after
a delay of about 5 ms. This delay is for card slot mechanism to settle down before power is actually
applied.
SCCLK starts to output clocks right after SCPWR# is active while SCIO is in reception mode and
pulled up externally. SCRST# keeps low initially to reset card but will output high after 512 clock cycles
to meet requirement of tb of more than 400 clock cycles (specified in ISO/IEC 7816-3).
相關PDF資料 |
PDF描述 |
|---|---|
| W83637HF-AW | LPC I/O |
| W83697HF | WINBOND I/O |
| W83697 | WINBOND I/O |
| W83697F | WINBOND I/O |
| W83697SF | WINBOND I/O |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W83637HF_06 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:LPC I/O |
| W83637HF-AW | 制造商:WINBOND 制造商全稱:Winbond 功能描述:LPC I/O |
| W83637HG | 制造商:WINBOND 制造商全稱:Winbond 功能描述:LPC I/O |
| W83637HG-AW | 功能描述:IC I/O CONTROLLER 128-QFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:* 標準包裝:3,000 系列:- 應用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| W83667HG-B | 制造商:Nuvoton Technology Corp 功能描述:LPC SUPER I/O, PECI 1.1A*, SST 制造商:Nuvoton Technology 功能描述:LPC SUPER I/O, PECI 1.1A*, SST |
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