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參數資料
型號： W83697HF
廠商： WINBOND ELECTRONICS CORP
元件分類： 外設及接口
英文描述： WINBOND I/O
中文描述： MULTIFUNCTION PERIPHERAL, PQFP128
封裝： PLASTIC, QFP-128
文件頁數： 55/167頁
文件大小： 1094K
代理商： W83697HF
W83697HF/F
Publication Release Date: Feb. 2002
- 46 - Revision 0.70
4.
UART PORT
4.1
Universal Asynchronous Receiver/Transmitter (UART A, UART B)
The UARTs are used to convert parallel data into serial format on the transmit side and convert serial
data to parallel format on the receiver side. The serial format, in order of transmission and reception, is
a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half (five-bit
format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65535 and producing a
16x clock for driving the internal transmitter logic. Provisions are also included to use this 16x clock to
drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore, the UARTs also
include complete modem control capability and a processor interrupt system that may be software
trailed to the computing time required to handle the communication link. The UARTs have a FIFO mode
to reduce the number of interrupts presented to the CPU. In each UART, there are 16-byte FIFOs for
both receive and transmit mode.
4.2
Register Address
4.2.1 UART Control Register (UCR) (Read/Write)
The UART
Control Register controls and defines the protocol for asynchronous data communications,
including data length, stop bit, parity, and baud rate selection.
2
3
4
5
6
7
0
1
Data length select bit 0 (DLS0)
Data length select bit 1(DLS1)
Multiple stop bits enable (MSBE)
Parity bit enable (PBE)
Even parity enable (EPE)
Parity bit fixed enable (PBFE)
Set silence enable (SSE)
Baudrate divisor latch access bit (BDLAB)
Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit binary
format) from the divisor latches of the baudrate generator during a read or write operation. When
this bit is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the Interrupt
Control Register can be accessed.
Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only IRTX is
affected by this bit; the transmitter is not affected.
Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1,
(1) if EPE is logical 1, the parity bit is fixed as logical 0 to transmit and check.
(2) if EPE is logical 0, the parity bit is fixed as logical 1 to transmit and check.
相關PDF資料
PDF描述
W83697 WINBOND I/O
W83697F WINBOND I/O
W83697SF WINBOND I/O
W83757 SUPER I/O CHIP
W83759 ADVANCED VL-IDE DISK CONTROLLER
相關代理商/技術參數
參數描述
W83697HF_05 制造商:WINBOND 制造商全稱:Winbond 功能描述:LPC I/O
W83697HG 功能描述:IC LPC SUPER I/O 128-PQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2
W83697SF 制造商:WINBOND 制造商全稱:Winbond 功能描述:WINBOND I/O
W83697UF 制造商:WINBOND 制造商全稱:Winbond 功能描述:LPC I/O
W83697UG 功能描述:IC LPC SUPER I/O 128-PQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2
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