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參數資料
型號: W83697HF
廠商: WINBOND ELECTRONICS CORP
元件分類: 外設及接口
英文描述: WINBOND I/O
中文描述: MULTIFUNCTION PERIPHERAL, PQFP128
封裝: PLASTIC, QFP-128
文件頁數: 68/167頁
文件大小: 1094K
代理商: W83697HF
W83697HF/F
Publication Release Date: Feb. 2002
Revision 0.70
- 59 -
5.1.6 Bank0.Reg5 - UART Line Status Register (USR)
Power on default <7:0> = 0000,0000 binary
Bit
7-3
2
Name
Read/Write
-
Read/Write
Description
Reserved
RX_TO
-
Set to 1 when receiver FIFO
or
frame status FIFO occurs
time-out. Read this bit will be cleared.
Received FIFO overrun. Read to clear.
This bit is set to a logical 1 to indicate received data are
ready to be read by the CPU in the RBR or FIFO. After no
data are left in the RBR or FIFO, the bit will be reset to a
logical 0.
1
0
OV_ERR
RDR
Read/Write
Read/Write
5.1.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG)
Power on default <7:0> = 0000,0000 binary
Bit
Name
Read/Write
Description
7-6
SMPSEL<1:0>
Read/Write
Sampling Mode Select. Select internal decoder
methodology from the internal filter. Selected decoder
mode will determine the receive data format. The sampling
mode is shown as bellow:
SMPSEL<1:0> = 00 T-Period Sample Mode.
SMPSEL<1:0> = 01 Over-Sampling Mode.
SMPSEL<1:0> = 10 Over-Sampling with re-sync.
SMPSEL<1:0> = 11 FIFO Test Mode.
The T-period code format is defined as follows.
(Number of bits) - 1
The Bit value is set to 0, then the high pulse will be
received. The Bit value is set to 1, then no energy will be
received. The opposite results will be generated when the
bit RXINV (Bank0.Reg6.Bit0) is set to 1.
B7 B6 B5 B4
B2 B1 B0
B3
Bit value
相關PDF資料
PDF描述
W83697 WINBOND I/O
W83697F WINBOND I/O
W83697SF WINBOND I/O
W83757 SUPER I/O CHIP
W83759 ADVANCED VL-IDE DISK CONTROLLER
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參數描述
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