
W83977F/ W83977AF
PRELIMINARY
Publication Release Date:March 1998
Preliminary Revision 0.58
-VII -
11.3.10 GPIO, ACPI, ROM Interface Timing Parameters..........................................................................153
12. TIMING WAVEFORMS...........................................................................................154
12.1 FDC......................................................................................................................................................154
12.2 UART/PARALLEL...............................................................................................................................155
12.2.1 Modem Control Timing...................................................................................................................156
12.3 PARALLEL PORT................................................................................................................................157
12.3.1 Parallel Port Timing.......................................................................................................................157
12.3.2 EPP Data or Address Read Cycle (EPP Version 1.9)......................................................................158
12.3.3 EPP Data or Address Write Cycle (EPP Version 1.9)......................................................................159
12.3.4 EPP Data or Address Read Cycle (EPP Version 1.7)......................................................................160
12.3.5 EPP Data or Address Write Cycle (EPP Version 1.7)......................................................................161
12.3.6 Parallel Port FIFO Timing.............................................................................................................161
12.3.7 ECP Parallel Port Forward Timing ................................................................................................162
12.3.8 ECP Parallel Port Reverse Timing .................................................................................................162
12.4 KBC......................................................................................................................................................163
12.4.1 Write Cycle Timing.........................................................................................................................163
12.4.2 Read Cycle Timing .........................................................................................................................163
12.4.3 Send Data to K/B............................................................................................................................163
12.4.4 Receive Data from K/B...................................................................................................................164
12.4.5 Input Clock.....................................................................................................................................164
12.4.6 Send Data to Mouse........................................................................................................................164
12.4.7 Receive Data from Mouse...............................................................................................................164
12.5 GPIO WRITE TIMING DIAGRAM......................................................................................................165
12.6 MASTER RESET (MR) TIMING .........................................................................................................165
12.7 ACPI.....................................................................................................................................................165
12.7.1
PANSW
Trigger and
PSCTRL
Timing.....................................................................................165
12.7.2
RIA
,
RIB
, KLCK, MCLK, PWAKIN1, PWAKIN2 Trigger and
PSCTRL
Timing.....................166
12.7.3
PHRI
Trigger and
PSCTRL
Timing..........................................................................................166
13. APPLICATION CIRCUITS.......................................................................................166
13.1 PARALLEL PORT EXTENSION FDD.................................................................................................166
13.2 PARALLEL PORT EXTENSION 2FDD...............................................................................................167
13.3 FOUR FDD MODE...............................................................................................................................167