
W83977F/ W83977AF
PRELIMINARY
Publication Release Date: March 1998
- 68 -
Revision 0.58
4.7.3 Set5.Reg3 - Sets Select Register (SSR)
Writing this register selects Register Set. Reading this register returns ECH.
Reg.
Bit 7
Bit 6
SSR
SSR7
SSR6
Default Value
1
1
Bit 5
SSR5
1
Bit 4
SSR4
0
Bit 3
SSR3
1
Bit 2
SSR2
1
Bit 1
SRR1
0
Bit 0
SRR0
0
4.7.4 Set5.Reg4 - Infrared Configure Register 1 (IRCFG1)
Reg.
IRCFG1
Reset Value
Bit 7
-
0
Bit 6
FSF_TH
0
Bit 5
FEND_M
0
Bit 4
AUX_RX
0
Bit 3
-
0
Bit 2
-
0
Bit 1
IRHSSL
0
Bit 0
IR_FULL
0
Bit 7:
Bit 6:
Reserved
, write 0.
FSF_TH - Frame Status FIFO Threshold
Set this bit to determine the frame status FIFO threshold level and to generate the
FSF_I. The threshold level values are defined as follows.
FSF_TH
0
1
Status FIFO Threshold Level
2
4
Bit 5:
FEND_MD - Frame End Mode
A write to 1 enables hardware to split data stream into equal length frame automatically
as defined in Set4.Reg4 and Set4.Reg5, i.e., TFRLL/TFRLH.
AUX_RX - Auxiliary Receiver Pin
A write to 1 selects IRRX input pin. (Refer to Set7.Reg7.Bit5)
Reserved
, write 0.
IRHSSL - Infrared Handshake Status Select
When set to 0, the HSR (Handshake Status Register) operates as same as defined in IR
mode. A write to 1 will disable HSR, and reading HSR returns 30H.
IR_FULL - Infrared Full Duplex Operation
When set to 0, IR module operates in half duplex. A write to 1 makes IR module operate
in full duplex.
Bit 4:
Bit 3~2:
Bit 1:
Bit 0:
4.7.5
Set5.Reg5 - Frame Status FIFO Register (FS_FO)
This register shows the bottom byte of frame status FIFO.
Reg.
Bit 7
Bit 6
FS_FO
FSFDR
LST_FR
Reset Value
0
0
Bit 5
-
0
Bit 4
MX_LEX PHY_ERR CRC_ERR
0
0
Bit 3
Bit 2
Bit 1
RX_OV
0
Bit 0
FSF_OV
0
0
Bit 7:
FSFDR - Frame Status FIFO Data Ready
Indicate that a data byte is valid in frame status FIFO bottom.
LST_FR - Lost Frame
Set to 1 when one or more frames have been lost.
Reserved
.
Bit 6:
Bit 5: