
W83977F/ W83977AF
PRELIMINARY
Publication Release Date: March 1998
- 62 -
Revision 0.58
Bit 4:
ALOOP - All Mode Loopback
A write to 1 will enable loopback in all modes.
D_CHSW - DMA TX/RX Channel Swap
If only one DMA channel operates in MIR/FIR mode, then the DMA channel can be
swapped.
D_CHSW
DMA Channel Selected
0
Receiver (Default)
1
Transmitter
A write to 1 will enable output data when ALOOP=1.
DMATHL - DMA Threshold Level
Set DMA threshold level as shown in the following table.
Bit 3:
Bit 2:
DMATHL
TX FIFO Threshold
16-Byte
13
23
RX FIFO Threshold
(16/32-Byte)
4
10
32-Byte
13
7
0
1
Bit 1:
DMA_F - DMA Fairness
DMA_F
Function Description
0
1
DMA request (DREQ) is forced inactive after 10.5us
No effect DMA request.
Bit 0:
ADV_SL - Advanced Mode Select
A write to 1 selects advanced mode.
4.4.3 Reg3 - Sets Select Register (SSR)
Reading this register returns E0H. Writing a value selects Register Set.
Reg.
Bit 7
Bit 6
SSR
SSR7
SSR6
Refault Value
1
1
Bit 5
SSR5
1
Bit 4
SSR4
0
Bit 3
SSR3
0
Bit 2
SSR2
0
Bit 1
SRR1
0
Bit 0
SRR0
0
4.4.4 Reg4 - Advanced IR Control Register 2 (ADCR2)
Mode
Bit 7
Bit 6
-
0
Bit 5
PR_DIV1 PR_DIV0 RX_FSZ1 RX_FSZ0 TX_FSZ1 TXFSZ0
0
0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Advanced IR DIS_BACK
Reset Value
0
0
0
0
Bit 7:
DIS_BACK - Disable Backward Operation
A write to 1 disables backward legacy IR mode. When operate in legacy SIR/ASK-IR
mode, this bit should be set to 1 to avoid backward operation.
Reserved,
write 0.
PR_DIV1~0 - Pre-Divisor 1~0.
These bits select pre-divisor for external input clock 24M Hz. The clock goes through the
pre-divisor then input to baud rate divisor of IR.
Bit 6:
Bit 5, 4:
PR_DIV1~0
00
01
10
11
Pre-divisor
13.0
1.625
6.5
1
Max. Baud Rate
115.2K
bps
921.6K
bps
230.4K
bps
1.5M
bps