
W83977F/ W83977AF
PRELIMINARY
Publication Release Date: March 1998
- 77 -
Revision 0.58
Bit 3:
Bit 2~0:
Reserved,
write 0.
HRC_SL2~0 - High Speed Remote IR Mode Select.
These bits setup the operational mode of
high speed
remote IR front-end module when
AM_FMT=1 and .AD_MD2~0 are configured to Remote IR mode. These values will be
automatically loaded to IR_SL2~0, respectively.
4.9.8 Set7.Reg7 - Infrared Module Control Register (IRM_CR)
Reg.
IRM_CR
Default Value
Bit 7
AM_FMT IRX_MSL
0
Bit 6
Bit 5
IRSL0D
0
Bit 4
RXINV
0
Bit 3
TXINV
0
Bit 2
-
0
Bit 1
-
0
Bit 0
-
0
0
Bit 7:
AM_FMT - Automatic Format
A write to 1 will enable automatic format IR front-end module. These bit will affect the
output of IR_SL2~0 which is referred by IR front-end module selection (Set7.Reg4~6)
IRX_MSL - IR Receiver Module Select
Select the receiver input path from the IR front end module if IR module has the
separated high speed and low speed receiver path. If the IR module has only one
receiving path, then this bit should be set to 0.
IRX_MSL
0
1
Bit 6:
Receiver Pin selected
IRRX (Low/High Speed)
IRRXH (High Speed)
Bit 5:
IRSL0D - Direction of IRSL0 Pin
Select function for IRRXH or IRSL0 because they share common pin and have different
input/output direction.
IRSL0_D
0
1
Function
IRRXH (I/P)
IRSL0 (O/P)
Table: IR receiver input pin selection
IRSL0D
0
0
0
0
1
1
1
1
IRX_MSL
0
0
1
1
0
0
1
1
AUX_RX
0
1
X
X
0
1
X
X
High Speed IR
X
X
0
1
X
X
0
1
Selected IR Pin
IRRX
IRRXH
IRRX
IRRXH
IRRX
Reserved
IRRX
Reserved
Note: that (1) AUX_RX is defined in Set5.Reg4.Bit4, (2) high speed IR includes MIR (1.152M or 0.576M bps) and FIR (4M bps), (3)
IRRX is the input of the low speed or high speed IR receiver, IRRXH is the input of the high speed IR receiver.
Bit 4:
RXINV - Receiving Signal Invert
A write to 1 will Invert the receiving signal.
TXINV - Transmitting Signal Invert
A write to 1 will Invert the transmitting signal.
Reserved,
write 0.
Bit 3:
Bit 2~0: