
W83977F/ W83977AF
PRELIMINARY
Publication Release Date:March 1998
Preliminary Revision 0.58
-IV -
4.9.7 Set7.Reg6 - Infrared Module (Front End) Select 3 (IRM_SL3)............................................................76
4.9.8 Set7.Reg7 - Infrared Module Control Register (IRM_CR)...................................................................77
5. PARALLEL PORT........................................................................................................78
5.1 PRINTER INTERFACE LOGIC...............................................................................................................78
5.2 ENHANCED PARALLEL PORT (EPP)....................................................................................................79
5.2.1 Data Swapper.....................................................................................................................................79
5.2.2 Printer Status Buffer...........................................................................................................................80
5.2.3 Printer Control Latch and Printer Control Swapper ...........................................................................80
5.2.4 EPP Address Port...............................................................................................................................81
5.2.5 EPP Data Port 0-3 .............................................................................................................................82
5.2.6 Bit Map of Parallel Port and EPP Registers.......................................................................................82
5.2.7 EPP Pin Descriptions.........................................................................................................................83
5.2.8 EPP Operation...................................................................................................................................83
5.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT.........................................................................84
5.3.1 ECP Register and Mode Definitions...................................................................................................84
5.3.2 Data and ecpAFifo Port......................................................................................................................85
5.3.3 Device Status Register (DSR)..............................................................................................................85
5.3.4 Device Control Register (DCR) ..........................................................................................................86
5.3.5 cFifo (Parallel Port Data FIFO) Mode = 010.....................................................................................87
5.3.6 ecpDFifo (ECP Data FIFO) Mode = 011............................................................................................87
5.3.7 tFifo (Test FIFO Mode) Mode = 110 ..................................................................................................87
5.3.8 cnfgA (Configuration Register A) Mode = 111....................................................................................87
5.3.9 cnfgB (Configuration Register B) Mode = 111....................................................................................87
5.3.10 ecr (Extended Control Register) Mode = all.....................................................................................88
5.3.11 Bit Map of ECP Port Registers.........................................................................................................89
5.3.12 ECP Pin Descriptions.......................................................................................................................90
5.3.13 ECP Operation.................................................................................................................................91
5.3.14 FIFO Operation................................................................................................................................91
5.3.15 DMA Transfers.................................................................................................................................92
5.3.16 Programmed I/O (NON-DMA) Mode ................................................................................................92
5.4 EXTENSION FDD MODE (EXTFDD).....................................................................................................92
5.5 EXTENSION 2FDD MODE (EXT2FDD).................................................................................................92
6. REAL-TIME CLOCK (RTC) AND "ON-NOW" CONTROL....................................93