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參數資料
型號: W88227F
廠商: WINBOND ELECTRONICS CORP
元件分類: 消費家電
英文描述: ATAPI CD-ROM Decoder(支持ATAPI標準的CD-ROM解碼器)
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP128
封裝: PLASTIC, QFP-128
文件頁數: 58/116頁
文件大小: 787K
代理商: W88227F
Preliminary/Confidential
Subject to change without notice
W88227F/W88227QD
- 54 -
1999/10/1 Rev: 0.70
When the drive becomes ready after BSY is cleared, the host starts to issue 12-byte ATAPI Command
Packet. Reception of the 6th packet word activates the following events.
FPKT (30h.r1)
1
TENDb (01h.r6)
0
Pin UINTb activate if
TENDEN (01h.w6)
has been enabled
Writing any value to register TACK (07h) deactivates APKT, TENDb, and corresponding interrupt.
Bit 6:
ADCEN - Automatic DRQ Clearing Enable
When this bit is high, DRQ (37h.3) is cleared to 0 and BSY (37h.7) is set to 1 after the end of
following transfers:
Host reads from external RAM
Host writes to Command Packet FIFO
ASCEN - Automatic Status Completion Enable
Bit 5:
When this bit is high, Status Completion is performed after the end of the following transfers:
Host reads from external RAM
Host write data to Packet FIFO, if
PFFSCB (01h.w3)
is low
ADCEN (18h.6)
should be enabled when ASCEN is enabled to provide clearing of DRQ (37h.3) and
setting of BSY (37h.7). If both ADCEN and ASCEN are enabled, the following hardware sequence is
executed at the end of one of the above data transfers:
Set BSY
DRQ (37h.3)
0
CHECK (37h.0)
ACHECK (3Eh.0)
CORR (37h.2)
ACORR (3Eh.2)
DRDY (37h.6)
ADRDY (3Eh.6)
ATINT (32h)
03h
Clear BSY
HIRQ (2Eh.3)
1
APKTEN (18h.7)
1, if AUTOEN (18h.4) is high
ASCEN (18h.5)
0
After detecting the interrupt, the host reads the ATAPI Status Register and if necessary, the Error
Register for the command completion status.
This bit is also cleared by setting
SCT (17h.w0)
high.
AUTOEN - Automatic APKTEN Set After Status Completion Enable
Bit 4:
When this bit is high, APKTEN (18h.7) will be set after Automatic Status Completion sequence
triggered by either SCT (17h.0) or ASCEN (18h.5).
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