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參數資料
| 型號： | W88227F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 消費家電 |
| 英文描述： | ATAPI CD-ROM Decoder(支持ATAPI標準的CD-ROM解碼器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數： | 65/116頁 |
| 文件大小： | 787K |
| 代理商： | W88227F |
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Preliminary/Confidential
Subject to change without notice
W88227F/W88227QD
- 61 -
1999/10/1 Rev: 0.70
TBH/L - Transfer Block Register - (read/write 25h/24h)
If
LATXF (03h.7)
is low,
TBH/L
form a 9-bit counter that is used to specify the first RAM block to be
transferred, while registers
TACH/L (05h/04h,w)
specify the starting address relative to the beginning of this
RAM block. The block-offset transfer is carried within a
transfer ring
that is controlled by
DTRCH/L
(53h/52h)
and
DTRBH/L (51h/50h)
. The buffer ring and transfer ring are usually defined in the same range.
Note that
TBH/L (25h/24h)
do not increment automatically at the end of each transfer unless:
DINB (1Fh.1)
is low (data-in transfer is enabled)
LATXF (03h.7)
is low (block-offset transfer is used)
If
ACMEN (9Ch.6)
is high,
TCC (9Dh)
minus
N
and
TBH/L (25h/24h)
plus
N
right after
SKIPC (9Eh)
is set
N
.
If
BICEN (9Ah.7)
is high and
BCFSEL (9Ah.5)
is low, the DSP buffering stop when buffering block (internal)
reach
TBK (9Bh,w)
.
SCBH/L - Subcode Block Register - (read/write 27h/26h)
SCBH/L (27h/26h)
form a 9-bit counter that contains the block number of the latest available subcode data that
can be read by the host. The number in
SCBH/L (27h/26h)
plus 1 points to the RAM block that is buffering
incoming subcode. The number in
SCBH/L (27h/26h)
increments at the end of subcode block buffering. If
SDBS (88h.4)
is high, the buffering of subcode is controlled by
DDBH/L (29h/28h)
rather than
SCBH/L
(27h/26h)
.
DDBH/L - Decoded Data Block Register - (read/write 29h/28h)
DDBH/L(29h/28h)
form a 9-bit counter that contains the number of the latest available decoded data block after
decoder interrupt occurs. CD-ROM sector data buffering is a block-based ring operation.
In
Real-Time-Correction (RTC)
mode, i.e.,
BICEN (9Ah.7)
is low, if the number in
DDBH/L (29h/28h)
is
N - 1
,
then the current sector is buffered into block with number
N
. The
DDBH/L (29h/28h)
increments at each sync.
When the decoded-block-number equals the value in
WBRCH/L (57h/56h)
, the sector is buffered into the block
with number specified by
WBRBH/L (55h/54h)
.
In
Buffer-Independent-Correction (BIC)
mode, i.e.,
BICEN (9Ah.7)
is low,
DDBH/L (29h/28h)
increments at the
end of EDC-checking if there is no
STAERR (80h.r6)
or
HCEI (80h.r0)
error.
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