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參數(shù)資料
型號(hào): W88227F
廠商: WINBOND ELECTRONICS CORP
元件分類: 消費(fèi)家電
英文描述: ATAPI CD-ROM Decoder(支持ATAPI標(biāo)準(zhǔn)的CD-ROM解碼器)
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP128
封裝: PLASTIC, QFP-128
文件頁(yè)數(shù): 78/116頁(yè)
文件大小: 787K
代理商: W88227F
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Preliminary/Confidential
Subject to change without notice
W88227F/W88227QD
- 74 -
1999/10/1 Rev: 0.70
GLCTL1 - Global Control Register 1 (read/write 43h)
The default of this register after hardware reset is 0x00h.
Bit 7:
RSTO - Pin RSTO output control
The state of
pin nRSTO
is the inverse value of this control bit. This bit is 0 after chip reset.
Bit 4:
UP323S - Pin UP323 Selection
UP323S (43h.4)
pin UP32/UP33
internal Decoder Interrupt
Remark
0b
INT0
INT1
(default)
1b
INT1
INT0
Bit 2:
CKOSTP: Pin CKO Output Stop
Setting this bit high immediately puts the output of
Pin CKO
at a steady "high" state. This bit is low
after master reset.
Bit 1:
ACLKS - ACLK Source Selection
Setting this bit high select pin DXI as ACLK input source. Setting this bit low select pin UXI as
ACLK input source. This bit is 0 after chip reset.
Bit 0:
DCLKS - DCLK Source Selection
Setting this bit high select pin DXI as DCLK input source. Setting this bit low select pin UXI as
DCLK input source. This bit is 0 after chip reset.
LSTA0-3 (read 48h-4Bh) - obsolete
LHD0-3 (read 4Ch-4Fh) - obsolete
Ring Control Registers - (read/write 50h to 57h)
These eight registers add flexibility to the block control of external memory that is controlled by
RTC2-0
(2Ah.2-0)
initially. Once one of these eight registers is set, all eight registers should be set to take full control
of block configuration of the external memory. The data-transfer-ring and write-buffer-ring are normally set
the same value.
DTRBL/DTRBH - Data Transfer Ring Base Register - (read/write 50h/51h)
Data Transfer Ring Base Register and Data Transfer Ring Ceiling Register treat the external memory as a ring
while transferring data to the host. Data Transfer Ring Base Register specifies the base block number of this
ring.
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