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參數(shù)資料
型號: W89C880F
廠商: WINBOND ELECTRONICS CORP
元件分類: 通信及網(wǎng)絡
英文描述: 100Base-Tx/T4 Multiport Repeater Controller(100Base-Tx/T4多端口中繼器控制器)
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP160
封裝: PLASTIC, QFP-160
文件頁數(shù): 13/26頁
文件大小: 313K
代理商: W89C880F
W89C880F FastMPR
Publication Release Date: January 1997
- 13 -
Revision A1
Carrier Integrity Monitor
The carrier integrity monitor function can be activated only in the 100BaseTX physical layer controller
(PHY) and is neglected in T4 PHY. The FastMPR monitors this carrier activity and utilizes four types
of timers to judge whether a carrier is distinguishable. The four timers are the false carrier timer (480
bits time), idle timer (33792 bits), Ipg timer (80 bits), and valid carrier timer (480 bits). The standard
IEEE802.3u specifications for these items are the following:
False carrier timer: 450
500 bit-time
Idle timer: 33000
±
25% bit-time
Ipg timer: 64
86 bit-time
Valid carrier timer: 450
500 bit-time
The carrier integrity monitor state machine will force a port to enter the isolation state to prevent a
malfunctioning port from disturbing the network segment. If the J and K patterns defined in 4B/5B
coding table occur, so that the carrier in the start of preamble is combined with so much noise that it
cannot be distinguished by the PHY controller, then PHY will put a false carrier packet on the MII bus.
If two consecutive false carrier events occur on a FastMPR port or a false carrier event occurs and
lasts for a time that exceeds the default value of the false timer register, the port will be forced into
isolation mode and its transmit/receive path will be inhibited.
A port in the isolation state will return to operating state when the medium is idle for more than the
summation of the set value of the idle timer and IPG timer or when both the carrier is absent and the
valid carrier timer has timed out.
PCS CODE
GROUP <4:0>
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
CODE
NAME
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
MII (TXD/RXD)
<3:0>
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
REMARK
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
Data 9
Data A
Data B
Data C
Data D
Data E
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