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參數資料
| 型號： | W89C880F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | 100Base-Tx/T4 Multiport Repeater Controller(100Base-Tx/T4多端口中繼器控制器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數： | 6/26頁 |
| 文件大小： | 313K |
| 代理商： | W89C880F |
W89C880F FastMPR
- 6 -
Pin Description, continued
PORT STATUS REPORT/JUMPER SETTING PINS
I/O
I/O/L
Any Collision status Output/Carrier Integrity Monitor Select. This is an
active high pin. After power-on reset, this pin outputs the FastMPR
port collision status (with the exception of the extension port).
O/L
Port Status Output select 0. After power-on reset, this output pin
latches the link/activity status report from the TP0
10RPT and
BTPRPT pins.
O/L
Port Status Output select 1. This output pin latches the partition
status report from the TP0
10RPT and BTPRPT pins.
O/L
Port Status Output select 2. This output pin latches the network
utilization report from the TP0
9RPT pins.
O/L
Port Status Output select 3. This output pin latches the jabber
status report from the TP0
10RPT, BTPRPT pins.
EXTENSION PORT INTERFACE PINS
I
Extension port Carrier Input. This is the carrier sense signal
coming from the FastMPR extension port. "1" means the
extension port has carrier present.
O/L
Extension port Transmit Enable Output. "1" means the extension
port is transmit enabled.
I
Extension port Receive Data. Input data from PHY connected to
bridge port. Data are synchronous with the rising edge of BRXC.
O/L
Extension port Transmit Data. Output data from FastMPR. Data
are synchronous with the rising edge of RTXC.
I
Extension port Receive Error. "1" means that an error has
occurred in the data received by PHY.
O/L
Extension port Transmit Error. "1" means that an RXER or FIFO
error event has occurred.
I
Extension port Receive Clock. Input from PHY. This pin is used to
synchronize the received data of PHY connected to the extension
port.
I
Extension port Receive Data Valid. Input from PHY. "1" means
PHY has valid data present on BRXD<3:0>.
I
Extension port Link Status Input. Input from PHY. "1" means PHY
link is good.
INTER-FastMPR INTERFACE PINS
5, 6, 8, 9
I/O/Z
Inter-FastMPR interface Data. These pins are used to cascade
several FastMPR chips into one larger unit. The FastMPRs use
the inter-FastMPR interface to send/receive data to/from other
FastMPRs. The data are transmitted in NRZ format. During idle
state, IDAT<3:0> are in high-impedance state.
NAME
XCOLRPT
NO.
151
DESCRIPTION
M0
155
M1
154
M2
153
M3
152
BCRS
58
BTXEN
56
BRXD
<3:0>
67
64
BTXD<3:0>
54
51
BRXER
60
BTXER
57
BRXC
62
BRXDV
59
BLINK
68
IDAT<3:0>
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