
W89C880F FastMPR
Publication Release Date: January 1997
- 7 -
Revision A1
Pin Description, continued
INTER-FastMPR INTERFACE PINS
NAME
IDCLK
NO.
11
I/O
I/O/Z
DESCRIPTION
Inter-FastMPR interface Data Clock. This is a bidirectional pin. If
the FastMPR issues a carrier output to the integrator through its
ICRS
pin, the integrator sends an acknowledge reply later
through the
IBEN
pin to the FastMPRs. Once an
ICRS
has been
issued and a valid
IBEN
has been received, the FastMPR sends
IDCLK, IJAM, and IDAT<3:0> to the inter-FastMPR interface
integrator. The other FastMPRs do not issue carrier outputs to the
integrator, but instead receive IDCLK, IJAM, and IDAT<3:0> from
the integrator after receiving valid
IBEN
. If
IBEN
is not asserted,
IDCLK is in high-impedance state.
IERR
4
I/O/Z
Inter-FastMPR interface Data Error. This pin indicates whether an
error occurred during a InterFastMPR interface transaction.
When the FastMPR transmits data to the inter-FastMPR interface
integrator, the assertion of IERR means a transmit error on the
interface occurred. When the FastMPR receives data from the
inter-FastMPR interface integrator, the assertion of IERR means
a receive error occurred on the interface.
ICRS
1
O/L
Inter-FastMPR interface Carrier Sense output. If asserted, the
FastMPR will output a packet to the inter-FastMPR interface
integrator. After the FastMPR that asserted
ICRS
receives a valid
IBEN
from the integrator, the FastMPR will send data to
IDAT<3:0>.
IBEN
2
I
Inter-FastMPR interface Enable. If asserted, the FastMPR that
issued
ICRS
earlier will output IDAT<3:0>, IDCLK, IJAM, and
IERR to the inter-FastMPR interface integrator.
ICOL
14
I
Inter-FastMPR interface Collision. "0" means a collision event
has occurred.
ICOL
is asserted only when more than one
FastMPR outputs a carrier to the inter-FastMPR interface
integrator at the same time.
Inter-FastMPR interface Jamming. When the FastMPR enters the
collision state, it asserts IJAM and propagates IJAM to the inter-
FastMPR interface integrator. When another FastMPR receives
IJAM from an integrator, it means that a collision has occurred on
the other FastMPR. When IJAM is asserted, the assertion of
IERR means the FastMPR is in the one_port_left state, and the
deassertion of IERR means the FastMPR is in the
multi_FastMPR collision state.
IJAM
13
I/O/Z