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參數資料
| 型號： | W89C880F |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | 100Base-Tx/T4 Multiport Repeater Controller(100Base-Tx/T4多端口中繼器控制器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數： | 14/26頁 |
| 文件大小： | 313K |
| 代理商： | W89C880F |
W89C880F FastMPR
- 14 -
Continued
11111
11000
10001
01101
00111
I
J
K
T
R
Undefined
0101
0101
Undefined
Undefined
IDLE; used as interstream fill code
Start-of-stream Delimiter
Start-of-sream Delimiter
End-of-sream Delimiter
End-of-sream Delimiter
4B/5B Code Group
MII Management
The FastMPR provides a set of configuration registers, accessible through the MDC and MDIO pins
on the MII serial management bus. The FastMPR can thus be managed through the MDC and MDIO
pins. For the FastMPR to be configured by programming these registers or setting hardware jumpers,
an external serial command generator is needed to generate an MII management frame format
command (shown in the following table) to drive MDC with a minimum 400 nS clock period so that
the data train is latched on the MDIO. The typical read and write timing of the serial interface is
shown in the diagram below (Figure 8 and Figure 9).
MII MANAGEMENT PROTOCOL
PHYAD
AAAAA
AAAAA
PRE
1... 1
1... 1
ST
01
01
OP
10
01
REGAD
RRRRR
RRRRR
TA
Z0
10
DATA
16 bits
16 bits
IDLE
Z
Z
Read
Write
Management Frame Format Table
Note:
PRE: Preample; ST: Start of Frame; OP: Operation code; PHYAD: PHY address; REGAD: register address.
TA: Turnaround.
Typical MDIO/MDC Read Cycle
high impedance(z)
z
....
Idle
Start Read
PHYAD
REGAD
TA
Data
Idle
1 0
Z 0
MDC
MDIO
....
Preamble
0 1
Figure 8
Typical MDIO/MDC Write Cycle
z
....
Idle
Start Write
PHYAD
REGAD
TA
Data
Idle
1 0
MDC
MDIO
....
Preamble
0 1 0 1
Figure 9
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