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參數資料
| 型號： | W28V400B |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 4M(512K x 8/256K x 16) SMARTVOLTAGE FLASH MEMORY |
| 中文描述： | 4分（為512k × 8/256K × 16）SMARTVOLTA通用閃存 |
| 文件頁數： | 23/48頁 |
| 文件大小： | 1822K |
| 代理商： | W28V400B |
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W28V400B/T
Publication Release Date: April 11, 2003
- 23 -
Revision A4
transitions to V
IL
during block erase or word/byte write, RY/#BY will remain low until the reset
operation is complete. Then, the operation will abort and the device will enter deep power-down. The
aborted operation may leave data partially altered. Therefore, the command sequence must be
repeated after normal operation is restored. Device power-off or #RESET transitions to V
IL
clear the
status register.
The CUI latches commands issued by system software and is not altered by V
PP
or #CE transitions or
WSM actions. Its state is read array mode upon power-up, after exit from deep power-down or after
V
DD
transitions below V
LKO
.
After block erase or word/byte write, even after V
PP
transitions down to V
PPLK
, the CUI must be placed
in read array mode via the Read Array command if subsequent access to the memory array is
desired.
Power-up/Down Protection
The device is designed to offer protection against accidental block erasure or word/byte writing during
power transitions. Upon power-up, the device is indifferent as to which power supply (V
PP
or V
DD
)
powers-up first. Internal circuitry resets the CUI to read array mode at power-up. A system designer
must guard against spurious writes for V
DD
voltages above V
LKO
when V
PP
is active. Since both #WE
and #CE must be low for a command write, driving either to V
IH
will inhibit writes. The CUI’s two-step
command sequence architecture provides added level of protection against data alteration.
#WP provide additional protection from inadvertent code or data alteration. The device is disabled
while #RESET = V
IL
regardless of its control inputs state.
Power Dissipation
When designing portable systems, designers must consider battery power consumption not only
during device operation, but also for data retention during system idle time. Flash memory’s non-
volatility increases usable battery life because data is retained when system power is removed.
In addition, deep power-down mode ensures extremely low power consumption even when system
power is applied. For example, portable computing products and other power sensitive applications
that use an array of devices for solid-state storage can consume negligible power by lowering
#RESET to V
IL
standby or sleep modes. If access is again needed, the devices can be read following
the t
PHQV
and t
PHWL
wake-up cycles required after #RESET is first raised to V
IH
.
See AC Characteristics
- Read Only and Write Operations and Figures 13, 14, 15 and 16 for more information.
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