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參數資料
| 型號： | W28V400B |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 4M(512K x 8/256K x 16) SMARTVOLTAGE FLASH MEMORY |
| 中文描述： | 4分（為512k × 8/256K × 16）SMARTVOLTA通用閃存 |
| 文件頁數： | 39/48頁 |
| 文件大小： | 1822K |
| 代理商： | W28V400B |
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W28V400B/T
Publication Release Date: April 11, 2003
- 39 -
Revision A4
V
DD
= 5V
±
0.5V, 5V
±
0.25V, T
A
= 0
°
C to +70
°
C
V
DD
= 5V
±
0.25V(5)
5V
±
0.5V(6)
PARAMETER
SYM.
Min.
Max.
Min.
Max.
UNIT
Write Cycle Time
t
AVAV
85
90
nS
#RESET High Recovery to #CE Going Low
(Note 2)
t
PHEL
1
1
μ
S
#WE Setup to #CE Going Low
t
WLEL
0
0
nS
#CE Pulse Width
t
ELEH
50
50
nS
#RESET V
HH
Setup to #CE Going High
(Note 2)
t
PHHEH
100
100
nS
#WP V
IH
Setup to #CE Going High (Note 2)
t
SHEH
100
100
nS
V
PP
Setup to #CE Going High (Note 2)
t
VPEH
100
100
nS
Address Setup to #CE Going High (Note 3)
t
AVEH
40
40
nS
Data Setup to #CE Going High (Note 3)
t
DVEH
40
40
nS
Data Hold from #CE High
t
EHDX
0
0
nS
Address Hold from #CE High
t
EHAX
5
5
nS
#WE Hold from #CE High
t
EHWH
0
0
nS
#CE Pulse Width High
t
EHEL
25
25
nS
#CE High to RY/#BY Going Low
t
EHRL
90
90
nS
Write Recovery before Read
t
EHGL
0
0
nS
V
PP
Hold from Valid SRD, RY/#BY High
(Note 2, 4)
t
QVVL
0
0
nS
#RESET V
HH
Hold from Valid SRD, RY/#BY
High (Note 2, 4)
T
QVPH
0
0
nS
#WP V
IH
Hold from Valid SRD, RY/#BY High
(Note 2, 4)
t
QVSL
0
0
nS
#BYTE Setup to #CE Going High (Note 7)
t
FVEH
40
40
nS
#BYTE Hold from #CE High (Note 7)
t
EHFV
85
90
nS
Notes:
1. In systems where #CE defines the write pulse width (within a longer #WE timing waveform), all setup, hold, and inactive #WE
times should be measured relative to the #CE waveform.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid AIN and DIN for block erase or word/byte write.
4. V
should be held at V
(and if necessary #RESET should be held at V
HH
) until determination of block erase or
word/byte write success (SR.1/3/4/5 = 0).
5. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed Configuration) for
testing characteristics.
6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration) for
testing characteristics.
7. If #BYTE switch during reading cycle, exist the regulations separately.
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