
Preliminary W79E225A/227A Data Sheet
Publication Release Date: December 14, 2007
- 137 -
Revision A2.0
In QEI mode, IC1 and IC0 work as QEB and QEA inputs respectively. QEA and QEB accept the
outputs from a quadrature encoded source, such as incremental optical shaft encoder. Two channels,
A and B, nominally 90 degrees out of phase, are required.
Noise
Filter
IC0/QEA
Noise
Filter
IC1/QEB
QEI
Control
Logic
MAXCNT/
Capture 2 register
PLSCNT/
Capture 1 register
PCNT/
Capture 0 register
Read access to
low byte of PCNT
Compare/Reload
Control Logic
Direction
Clock
Mode
Select bits
Noise
Filter
IC2
Figure 15-10: QEI Block Diagram
The QEI control logic detects the relation of phase lead/lag between QEA and QEB to produce
direction index (DIR) and clock to control pulse counter. The comparator/reload logic compares the
pulse counter and maximum count and control the function of reloading pulse counter in compare-
counting mode. In Free-counting mode, the pulse counter will counts until the 65535 value. In
Compare-counting mode, the pulse counter will count to MAXCNT value.
The value of the pulse
counter is not affected during QEI mode changes, nor when the QEI is disabled altogether.
In QEI mode, when IC2 edge (rising/falling edge is programmable through CAPCON0) has been
detected, CPTF2 will be set (if QEIEN=ICEN2=1 and DISIDX=0), and the only way to clear it is by
software.