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參數資料
| 型號： | W79E227A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數： | 87/200頁 |
| 文件大小： | 3644K |
| 代理商： | W79E227A |
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Preliminary W79E225A/227A Data Sheet
Publication Release Date: December 14, 2007
- 87 -
Revision A2.0
9. POWER MANAGEMENT
The W79E225/227 provides idle mode and power-down mode to control power consumption. These
modes are discussed in the next two sections.
9.1 Idle Mode
The user can put the device into idle mode by writing 1 to the bit PCON.0. The instruction that sets the
idle bit is the last instruction that will be executed before the device goes into Idle Mode. In the Idle
mode, the clock to the CPU is halted, but not to the Interrupt, Timer, Watchdog timer, PWM, ADC and
Serial ports blocks. This forces the CPU state to be frozen; the Program counter, the Stack Pointer,
the Program Status Word, the Accumulator and the other registers hold their contents. The ALE and
PSEN
pins are held high during the Idle state. The port pins hold the logical states they had at the time
Idle was activated. The Idle mode can be terminated in two ways. Since the interrupt controller is still
active, the activation of any enabled interrupt can wake up the processor. This will automatically clear
the Idle bit, terminate the Idle mode, and the Interrupt Service Routine (ISR) will be executed. After the
ISR, execution of the program will continue from the instruction which put the device into Idle mode.
The Idle mode can also be exited by activating the reset. The device can be put into reset either by
applying a high on the external RST pin, a Power on reset condition or a Watchdog timer reset. The
external reset pin has to be held high for at least two machine cycles i.e. 8 clock periods to be
recognized as a valid reset. In the reset condition the program counter is reset to 0000h and all the
SFRs are set to the reset condition. Since the clock is already running there is no delay and execution
starts immediately. In the Idle mode, the Watchdog timer continues to run, and if enabled, a time-out
will cause a watchdog timer interrupt which will wake up the device. The software must reset the
Watchdog timer in order to preempt the reset which will occur after 512 clock periods of the time-out.
When the device is exiting from an Idle mode with a reset, the instruction following the one which put
the device into Idle mode is not executed. So there is no danger of unexpected writes.
9.2 Power Down Mode
The device can be put into Power Down mode by writing 1 to bit PCON.1. The instruction that does
this will be the last instruction to be executed before the device goes into Power Down mode. In the
Power Down mode, all the clocks are stopped and the device comes to a halt. All activity is completely
stopped and the power consumption is reduced to the lowest possible value. In this state the ALE and
PSEN
pins are pulled low (if PWDNH=0). The port pins output the values held by their respective
SFRs.
The device will exit the Power Down mode with a reset or by an external interrupt pin enabled
(external interrupts 0 and 1). An external reset can be used to exit the Power down state. The high on
RST pin terminates the Power Down mode, and restarts the clock. The program execution will restart
from 0000h. In the Power down mode, the clock is stopped, so the Watchdog timer cannot be used to
provide the reset to exit Power down mode.
The device can be waken up from the Power Down mode by forcing an external interrupt pin
activation, provided the corresponding interrupt is enabled, while the global enable (EA) bit is set. If
these conditions are met, then either a low-level or a falling-edge at external interrupt pin will re-start
the oscillator. The device will then execute the interrupt service routine for the corresponding external
interrupt. After the interrupt service routine is completed, the program execution returns to the
instruction after one which put the device into Power Down mode and continues from there.
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