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參數(shù)資料
| 型號： | W79E227A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 145/200頁 |
| 文件大小： | 3644K |
| 代理商： | W79E227A |
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Preliminary W79E225A/227A Data Sheet
Publication Release Date: December 14, 2007
- 145 -
Revision A2.0
The FE bit is set to 1 by the hardware, but it must be cleared by the software. Once FE is set, any
frames received afterwards, even those without errors, do not clear the FE flag. The flag has to be
cleared by the software. Note that SMOD0 must be set to 1 while reading or writing FE.
16.6 Multiprocessor Communications
Multiprocessor communication is available in modes 1, 2 and 3 and makes use of the 9th data bit and
the automatic address recognition feature. This approach eliminates the software overhead required to
check every received address and greatly simplifies the program.
In modes 2 and 3, address bytes are distinguished from data bytes by 9th bit set, which is set high in
address bytes. When the master processor wants to transmit a block of data to one of the slaves, it
first sends the address of the target slave(s). The slave processors have already set their SM2 bits
high so that they are only interrupted by an address byte. The automatic address recognition feature
then ensures that only the addressed slave is actually interrupted. This feature compares the received
byte to the slave’s Given or Broadcast address and only sets the RI flag if the bytes match. This slave
then clears the SM2 bit, clearing the way to receive the data bytes. The unaddressed slaves are not
affected, as they are still waiting for their address.
In mode 1, the 9th bit is the stop bit, which is 1 in valid frames. Therefore, if SM2 is 1, RI is only set if a
valid frame is received and if the received byte matches the Given or Broadcast address.
The master processor can selectively communicate with groups of slaves using the Given Address or
all the slaves can be addressed together using the Broadcast Address. The addresses for each slave
are defined by the SADDR and SADEN registers. The slave address is the 8-bit value specified in
SADDR. SADEN is a mask for the value in SADDR. If a bit position in SADEN is 0, then the
corresponding bit position in SADDR is a don't-care condition in the address comparison. Only those
bit positions in SADDR whose corresponding bits in SADEN are 1 are used to obtain the Given
Address. This provides flexibility to address multiple slaves without changing addresses in SADDR.
The following example shows how to setup the Given Addresses to address different slaves.
Slave 1:
SADDR 1010 0100
SADEN 1111 1010
Given 1010 0x0x
Slave 2:
SADDR 1010 0111
SADEN 1111 1001
Given 1010 0xx1
The Given Address for slaves 1 and 2 differ in the LSB. In slave 1, it is a don't-care, while, in slave 2, it
is 1. Thus, to communicate with only slave 1, the master must send an address with LSB = 0 (1010
0000). Similarly, bit 1 is 0 for slave 1 and don't-care for slave 2. Hence, to communicate only with
slave 2, the master has to transmit an address with bit 1 = 1 (1010 0011). If the master wishes to
communicate with both slaves simultaneously, then the address must have bit 0 = 1 and bit 1 = 0.
Since bit 3 is don't-care for both slaves, two different addresses can address both slaves (1010 0001
and 1010 0101).
The master can communicate with all the slaves simultaneously using the Broadcast Address. The
Broadcast Address is formed from the logical OR of the SADDR and SADEN registers. The zeros in
the result are don't–care values. In most cases, the Broadcast Address is FFh. In the previous case,
the Broadcast Address is (1111111X) for slave 1 and (11111111) for slave 2.
The SADDR and SADEN registers are located at addresses A9h and B9h, respectively. These two
registers default to 00h, so the Given Address and Broadcast Address default to XXXX XXXX (i.e., all
bits don't-care), which effectively removes the multiprocessor communications feature
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