
Preliminary W79E225A/227A Data Sheet
Publication Release Date: December 14, 2007
- 61 -
Revision A2.0
BIT
NAME
FUNCTION
7-0
PWMxB
0 = The PWM0 output is low, when Brake is asserted.
1 = The PWM0 output is high, when Brake is asserted.
Note: x = 0~7
ACCUMULATOR
Bit:
7
6
5
4
3
2
1
0
ACC.7
ACC.6
ACC.5
ACC.4
ACC.3
ACC.2
ACC.1
ACC.0
Mnemonic: ACC
Address: E0h
BIT
NAME
FUNCTION
7-0
ACC
The A or ACC register is the standard 8032 accumulator
ADC CONTROL REGISTER
Bit:
7
6
5
4
3
2
1
0
ADCEN
-
ADCEX
ADCI
ADCS
AADR.2
AADR.1
AADR.0
Mnemonic: ADCCON
Address: E1h
BIT
7
6
NAME
ADCEN
-
FUNCTION
Enable A/D Converter Function. Set ADCEN to logic high to enable ADC block.
Reserved.
Enable external start control of ADC conversion by a rising edge from P4.0.
ADCEX=0: Disable external start. ADCEX=1: Enable external start control.
A/D Converting Complete/Interrupt Flag. This flag is set when ADC conversion is
completed. The ADC interrupt is requested if the interrupt is enabled. ADCI is set
by hardware and cleared by software only.
ADC Start and Status: Set this bit to start an A/D conversion. It may also be set
by STADC if ADCEX is 1. This signal remains high while the ADC is busy and is
reset right after ADCI is set.
Notes:
1.
It is recommended to clear ADCI
before
ADCS is set. However, if ADCI is
cleared and ADCS is set at the same time, a new A/D conversion may start
on the same channel.
2.
Software clearing of ADCS will abort conversion in progress.
3.
ADC cannot start a new conversion while ADCS or ADCI is high.
Select and enable analog input channel from ADC0 to ADC7.
AADR[2:0]
ADC selected input
AADR[2:0]
000
ADCCH0 (P1.0)
001
ADCCH1 (P1.1)
010
ADCCH2 (P1.2)
011
ADCCH3 (P1.3)
5
ADCEX
4
ADCI
3
ADCS
2-0
AADR
ADC selected input
ADCCH4 (P1.4)
ADCCH5 (P1.5)
ADCCH6 (P1.6)
ADCCH7 (P1.7)
100
101
110
111