
Preliminary W79E225A/227A Data Sheet
Publication Release Date: December 14, 2007
- 39 -
Revision A2.0
PORT 4 CHIP-SELECT POLARITY
Bit:
7
6
5
4
3
2
1
0
P43INV
P42INV
P41INV
P40INV
-
PWDNH
RMWFP
PUP0
Mnemonic: P4CSIN
Address: A2h
BIT
NAME
FUNCTION
7-4
P4xINV
The Active Polarity of P4.x when it is set as a chip-select strobe output. High =
Active High. Low = Active Low. Note: x = 3,2,1,0.
Reserved.
Set PWDNH to logic 1 then ALE and PSEN will keep high state, clear this bit to
logic 0 then ALE and PSEN will output low during power down mode.
Control Read Path of Instruction “Read-Modify-Write”. When this bit is set, the
read path of executing “read-modify-write” instruction is from port pin otherwise
from SFR.
Enable Port 0 weak pull up.
3
-
2
PWDNH
1
RMWFP
0
PUP0
CAPTURE CONTROL 0 REGISTER
Bit:
7
6
5
4
3
2
1
0
CCT2.1
CCT2.0
CCT1.1
CCT1.0
CCT0.1
CCT0.0
CCLD1
CCLD0
Mnemonic: CAPCON0
Address: A3h
BIT
NAME
FUNCTION
7-6
CCT2.1-0
Capture 2 edge select.
CCT2.1 CCT2.0
0
0
1
1
Description
0
1
0
1
Rising edge trigger
Falling edge trigger
Rising and falling edge trigger
Reserved.
5-4
CCT1.1-0
Capture 1 edge select.
CCT1.1 CCT1.0
0
0
1
1
Description
0
1
0
1
Rising edge trigger
Falling edge trigger
Rising and falling edge trigger
Reserved.
3-2
CCT0.1-0
Capture 0 edge select.
CCT0.1 CCT0.0
0
0
1
1
Description
0
1
0
1
Rising edge trigger
Falling edge trigger
Rising and falling edge trigger
Reserved.