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參數(shù)資料
| 型號： | W971632AF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 256K x 32 bit x 2 Banks SGRAM(256K x 32位 x 2組同步圖形RAM) |
| 中文描述： | 256K × 32位× 2銀行SGRAM（256K × 32位× 2組同步圖形RAM）的 |
| 文件頁數(shù)： | 13/55頁 |
| 文件大小： | 2653K |
| 代理商： | W971632AF |
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W971632AF
256K x 32 bit x 2 Banks SGRAM
Revision 1.0 Publication Release Date: March, 1999
- 13 -
Auto-Precharge Command
If A8 is set to high when the Read or Write Command is issued, then the auto-precharge function is entered. During
autoprecharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge
automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of
clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS latency.
A Read or Write Command with auto-precharge can not be interrupted before the entire burst operation is completed. Therefore,
use of a Read, Write, or Precharge Command is prohibited during a read or write cycle with auto-precharge. Once the precharge
operation has started, the bank cannot be reactivated until the Precharge time (t
RP
) has been satisfied. Issue of Auto-Precharge
command is illegal if the burst is set to full page length. If A8 is high when a Write Command is issued, the Write with Auto-
Precharge function is initiated. The SGRAM automatically enters the precharge operation one clock delay from the last burst
write cycle. This delay is referred to as Write tDPL. The bank undergoing auto-precharge can not be reactivated until tDPL and t
RP
are satisfied. This is referred to as t
DAL
, Data-in to Active delay (t
DAL
= t
DPL
+ t
RP
). When using the Auto-precharge Command, the
interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy t
RAS
(min).
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when
CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge
each bank separately or all banks simultaneously. Two address bits, A10, and A8, are used to define which bank(s) is to be
precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated before
a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be
greater than or equal to the Precharge time (t
RP
).
Self Refresh Command
The Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock.
All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to
keep the device in Self Refresh mode. When the SGRAM has entered Self Refresh mode all of the external control signals, except
CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self
Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation
and before the next command can be issued. This delay is equal to the RAS cycle time plus the Self Refresh exit time.
Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the
power. The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down
mode longer than the Refresh period (t
REF
) of the device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next
rising clock edge, depending on t
CK
. The input buffers need to be enabled with CKE held high for a period equal to t
CES
(min) +
t
CK
(min).
No Operation Command
The No Operation Command should be used in cases when the SGRAM is in a idle or a wait state to prevent the SGRAM from
registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS,
CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is
still executing, such as a burst read or write cycle.
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