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參數資料
| 型號： | W971632AF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 256K x 32 bit x 2 Banks SGRAM(256K x 32位 x 2組同步圖形RAM) |
| 中文描述： | 256K × 32位× 2銀行SGRAM（256K × 32位× 2組同步圖形RAM）的 |
| 文件頁數： | 14/55頁 |
| 文件大小： | 2653K |
| 代理商： | W971632AF |
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W971632AF
256K x 32 bit x 2 Banks SGRAM
Revision 1.0 Publication Release Date: March, 1999
- 14 -
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought
high, the RAS, CAS, and WE signals become don't cares.
Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low while at least one of the
banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends any
clocked operation that was currently being executed. There is a one clock delay between the registration of CKE low and the time
at which the SGRAM operation suspends. While in Clock Suspend mode, the SGRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high
to when Clock Suspend mode is exited.
DEFINE SPECIAL FUNCTION (DSF)
The DSF controls the graphic applications of SGRAM. If DSF is tied to low, SGRAM functions as 256K x 32 x2 Bank SDRAM.
SGRAM can be used as an unified memory by the appropriate DSF command. All the graphic function mode can be entered only
by setting DSF high when issuing commands which otherwise would be normal SDRAM commands. SDRAM functions such as
RAS Active, Write, and WCBR change to SGRAM functions such as RAS Active with WPB, Block Write and SWCBR
respectively. See sessions below for the graphic functions that DSF control.
SPECIAL MODE REGISTER SET (SMRS)
There are two kinds of special mode registers in SGRAM.One is color register and the other is mask register. Those usages will
be explained at "WRITE PER BIT" and "BLOCK WRITE" session. When A5 and DSF goes high in the same cycle as CS, RAS,
CAS and WE going low, load mask register (LMR) process is executed and the mask registers are filled with the masks for
associated DQ’s through DQ pins. And when A 6 and DSF goes high in the same cycle as CS, RAS, CAS and WE going low,
load color register(LCR) process is executed and the color register is filled with color data for associated DQ’s through the DQ
pins. The next clock of LMR or LCR, a new command can be issued. Special Mode Rregister Set, compared with Mode Rregister
Set, can be issued at the active state under the condition that DQ’s are idle. As in write operation, Special Mode Rregister Set
accepts the data needed through DQ pins. Therefore it should be attended not to induce bus contention. The more detailed
materials can be obtained by referring corresponding timing diagram.
WRITE PER BIT
Write Per Bit (i.e. I/O mask mode) for SGRAM is a function that selectively masks bits of data being written to the devices. The
mask is stored in an internal register and applied to each bit of data written when enabled. Bank active command with DSF=High
enabled write per bit for associated bank. Bank active command with DSF=Low disables write per bit for the associ-ated bank.
The mask used for write per bit operations is stored in the mask register accessed by SWCBR (Special Mode Register Set
Command). When a mask bit=1, the associated data bit is written when a write command is executed and write per bit has been
enabled for the bank being written. When a mask bit=0, the associated data bit is unaltered when a write command is executed
and the write per bit has been enabled for the bank being written. No additional timing conditions are required for write per bit
operations. Write per bit writes can be either single write, burst writes or block writes. DQM masking is the same for write per bit
and non Write Per Bit write.
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