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參數資料
| 型號： | W741E260 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT FLASH MICROCONTROLLER |
| 中文描述： | 4-BIT, FLASH, 4.19 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數： | 10/94頁 |
| 文件大小： | 554K |
| 代理商： | W741E260 |
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W741E260
- 10 -
Clock Generator
The W741E260 provides two oscillation circuits, main-oscillator and sub-oscillator. The main-oscillator
can select the crystal or RC oscillation circuit by option codes to generate the system clock through
external connections. If a crystal oscillator is used, a crystal or a ceramic resonator must be connected
to XIN1 and XOUT1, and a capacitor must be connected if an accurate frequency is needed. When the
oscillator is used, a high-frequency clock (400 KHz to 4 MHz) or low-frequency clock (32 KHz) can be
selected for the system clock by means of option codes. If the RC oscillator is used, a resistor must be
connected to XIN1 and XOUT1, and the high/low frequency clock option must be selected to suit the
operation frequency. The sub-oscillator must be connected to a 32.768 KHz crystal through XIN2 and
XOUT2 external pins when the dual-clock operation mode is selected by option code. The connection
is shown in Figure 3. One machine cycle consists of a four-state system clock sequence and can run
up to 1
μ
S with a 4 MHz system clock.
XIN1
XOUT1
XIN2
XOUT2
or
32 KHz or
400K to 4MHz
Crystal
Crystal
32 KHz
Resistor
Figure 3. System Clock Oscillator Configuration
Dual-clock operation
This operation mode is selected by code option. In the dual-clock mode, the clock source of the LCD
frequency selector should be the sub-oscillator clock (32768 Hz) only. But in the single-clock mode, the
clock source of the LCD frequency selector will be Fm or Fm/32 (Fm: main oscillator clock). So when
the STOP instruction is executing, the LCD will be turned off in the single-clock mode; but the LCD will
keep working in the dual-clock mode.
In this dual-clock mode, the normal operation is performed by generating the system clock from the
main-oscillator clock (Fm). As required, the slow operation can be performed by generating the system
clock from the sub-oscillator clock (Fs). The exchange of the normal operation and the slow operation
is performed by resetting or setting the bit 0 of the system clock control register (SCR). If the SCR.0 is
reset to 0, the clock source of the system clock generator is the main-oscillator clock; if the SCR.0 is
set to 1, the clock source of the system clock generator is the sub-oscillator clock. In the dual-clock
mode, the main-oscillator can stop oscillating when the STOP instruction is executing or the SCR.1 is
set to 1. But in the single-clock mode, only the STOP instruction can stop the main-oscillator
oscillating, because the SCR would be disabled in the single-clock mode. Therefore, in single-clock
mode, the clock source of the system clock generator is the main-oscillator clock (F
OSC
= Fm).
When the SCR is set or reset, we must pay attention to the following:
1. X000B
→
X011B: Disable the main-oscillator (Fm) should not be done simultaneously with changing
the system clock source (F
OSC
) from Fm to Fs. The F
OSC
should be changed first from Fm to Fs
before the main-oscillator (Fm) is disabled. The correct sequence is: X000B
→
X001B
→
X011B.
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