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參數資料
| 型號： | W741E260 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT FLASH MICROCONTROLLER |
| 中文描述： | 4-BIT, FLASH, 4.19 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數： | 19/94頁 |
| 文件大小： | 554K |
| 代理商： | W741E260 |
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W741E260
Publication Release Date: March 1998
- 19 -
Revision A2
Bit 0 = 0 RB.0 works as output pin; Bit 0 = 1 RB.0 works as input pin
Bit 1 = 0 RB.1 works as output pin; Bit 1 = 1 RB.1 works as input pin
Bit 2 = 0 RB.2 works as output pin; Bit 2 = 1 RB.2 works as input pin
Bit 3 = 0 RB.3 works as output pin; Bit 3 = 1 RB.3 works as input pin
At initial reset, the port RB is input mode (PM2 = 1111B).
Input Ports RC & RD
Port RC consists of pins RC.0 to RC.3, and port RD consists of pins RD.0 to RD.3. Each pin of port RC
and port RD can be connected to a pull-up resistor, which is controlled by the port mode 0 register
(PM0). When the PEF, HEF, and IEF corresponding to the RC port are set, a signal change on the
specified pins of port RC will execute the hold mode release or interrupt subroutine. Port status register
0 (PSR0) records the status of ports RC, i.e., any signal changes on the pins that make up the port.
PSR0 can be read out and cleared by the MOV R, PSR0, and CLR PSR0 instructions. In addition, the
falling edge signal on the pin of port RC specified by the instruction MOV SEF, #I will cause the device
to exit the stop mode
.
Refer to Figure 9 and the instruction table for more details. The RD port is used
as input port only, it has no hold mode release, wake-up stop mode or interrupt functions.
Port Status Register 0 (PSR0)
Port status register 0 is organized as 4-bit binary register (PSR0.0 to PSR0.3). PSR0 can be read or
cleared by the MOVA R, PSR0, and CLR PSR0 instructions. The bit descriptions are as follows:
R
R
R
R
0
1
2
3
PSR0
Note: R means read only.
Bit 0 = 1 Signal change at RC.0
Bit 1 = 1 Signal change at RC.1
Bit 2 = 1 Signal change at RC.2
Bit 3 = 1 Signal change at RC.3
Port Enable Flag (PEF)
The port enable flag is organized as 4-bit binary register (PEF.0 to PEF.3). Before port RC may be
used to release the hold mode or perform interrupt function, the content of the PEF must be set first.
The PEF is controlled by the MOV PEF, #I instruction. The bit descriptions are as follows:
PEF
w
w
w
0
1
2
w
3
Note: W means write only.
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