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參數資料
型號: W741E260
廠商: WINBOND ELECTRONICS CORP
元件分類: 微控制器/微處理器
英文描述: 4-BIT FLASH MICROCONTROLLER
中文描述: 4-BIT, FLASH, 4.19 MHz, MICROCONTROLLER, PQFP80
封裝: QFP-80
文件頁數: 13/94頁
文件大小: 554K
代理商: W741E260
W741E260
Publication Release Date: March 1998
- 13 -
Revision A2
Q1
Q2
Q9
Q10 Q11 Q12
Q14
Q13
Fosc
S
R
Q
HEF.0
IEF.0
1. Reset
2. CLR EVF, #01H
3. CLR DIVR0
EVF.0
Hold mode release (HCF.0)
Divider0 interrupt (INT0)
...
Overflow signal
WDT
Enable
/Disable
PMF.3
Fosc/1024
Fosc/16384
Mask Option
Qw1
R
Qw2
R
Qw4
R
Qw3
R
Divider0
System Reset
1. Reset
2. CLR WDT
R
R
R
R
Figure 5. Organization of Divider0 and Watchdog Timer
Parameter Flag (PMF)
The parameter flag is organized as a 4-bit binary register (PMF.0 to PMF.3). The PMF is controlled by
the SET PMF, #I or CLR PMF, #I instruction. The bit descriptions are as follows:
Note: W means write only.
W
0
1
2
3
PMF
Bit 0, Bit1, Bit2 Reserved
Bit 3 = 0 The fundamental frequency of the watchdog timer is F
OSC
/1024.
= 1 The fundamental frequency of the watchdog timer is F
OSC
/16384.
Timer/Counter
1. Timer 0 (TM0)
Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be loaded into
TM0 by executing the MOV TM0L (TM0H), R or MOV TM0, #I instructions. When the MOV TM0L
(TM0H), R instructions are executed, the TM0 will stop down-counting (if the TM0 is down-counting),
the MR0.3 will be reset to 0, and the specified value is loaded into TM0. If MR0.3 is set to 1, the event
flag 1 (EVF.1) is reset and the TM0 starts to count. When it decrements to FFH, Timer 0 stops
operating and generates an underflow (EVF.1 = 1). The interrupt is executed if the Timer 0 interrupt
enable flag has been set (IEF.1 = 1); and the hold state is terminated if the hold release enable flag 1
has been set (HEF.1 = 1). The Timer 0 clock input can be set as F
OSC
/1024 or F
OSC
/4 by setting
MR0.0 to 1 or by resetting MR0.0 to 0. The default timer value is F
OSC
/4. The organization of Timer 0
is shown in Figure 6.
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