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參數資料
| 型號： | W741E260 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT FLASH MICROCONTROLLER |
| 中文描述： | 4-BIT, FLASH, 4.19 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數： | 12/94頁 |
| 文件大小： | 554K |
| 代理商： | W741E260 |
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W741E260
- 12 -
Dual clock operation mode:
- Sub-oscillator enable
- SCR.0 = 0, F
OSC
= Fm
- Flcd = Fs, in STOP mode LCD work continue
Single clock operation mode:
- Sub-oscillator disable
- SCR not use, Main oscillator enable, F
OSC
= Fm
- Flcd = F
OSC
(F
OSC
/32), in STOP mode LCD off
Divider
Each divider is organized as a 14-bit binary up-counter designed to generate periodic interrupts. When
the main oscillator starts action, the Divider0 is incremented by each clock (F
OSC
). When an overflow
occurs, the Divider0 event flag is set to 1 (EVF.0 = 1). The interrupt is executed if the Divider0 interrupt
enable flag has been set (IEF.0 = 1), and the hold state is terminated if the hold release enable flag
has been set (HEF.0 = 1). The last 4-stage of the Divider0 can be reset by executing a CLR DIVR0
instruction. If the main oscillator is connected to the 32768 Hz crystal, the EVF.0 will be set to 1
periodically at each 500 mS interval.
If the sub-oscillator is enabled, the Divider1 is incremented by each clock (Fs). When an overflow
occurs, the Divider1 event flag is set to 1 (EVF.4 = 1). The interrupt is executed if the Divider1 interrupt
enable flag has been set (IEF.4 = 1), and the hold state is terminated if the hold release enable flag
has been set (HEF.4 = 1). There are two time periods (250 mS & 500 mS) that can be selected by
setting the SCR.3 bit. When SCR.3 = 0 (default), the 500 mS period time is selected; when SCR.3 = 1,
the 250 mS period time is selected.
Watchdog Timer (WDT)
The watchdog timer (WDT) is organized as a 4-bit up counter and is designed to protect the program
from unknown errors. The WDT is enabled when the corresponding option code bit of the WDT is set
to 1. If the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is
F
OSC
/1024. The input clock of the WDT can be switched to F
OSC
/16384 (or F
OSC
/1024) by executing
the SET PMF, #08H (or CLR PMF, #08H) instruction. The contents of the WDT can be reset by the
instruction CLR WDT. In normal operation, the application program must reset WDT before it
overflows. A WDT overflow indicates that the operation is not under control and the chip will be reset.
The WDT minimun overflow period is 468.75 mS when the system clock (F
OSC
) is 32 KHz and WDT
clock input is F
OSC
/1024. When the corresponding option code bit of the WDT is set to 0, and the
WDT function is disabled. The organization of the Divider0 and watchdog timer is shown in Figure 5.
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