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參數資料
| 型號： | W741E260 |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT FLASH MICROCONTROLLER |
| 中文描述： | 4-BIT, FLASH, 4.19 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數： | 17/94頁 |
| 文件大小： | 554K |
| 代理商： | W741E260 |
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W741E260
Publication Release Date: March 1998
- 17 -
Revision A2
Bit 0 = 0 The internal fundamental frequency of Timer 1 is F
OSC
.
= 1 The internal fundamental frequency of Timer 1 is F
OSC
/64.
Bit 1 = 0 The fundamental frequency source of Timer 1 is the internal clock.
= 1 The fundamental frequency source of Timer 1 is the external clock from RC.0 input pin.
Bit 2 = 0 The specified waveform of the MFP generator is delivered at the MFP output pin.
= 1 The specified frequency of Timer 1 is delivered at the MFP output pin.
Bit 3 = 0 Timer 1 stops down-counting.
= 1 Timer 1 starts down-counting.
Input/Output Ports RA, RB
Port RA consists of pins RA.0 to RA.3 and Port RB consists of pins RB.0 to RB.3. At initial reset,
input/output ports RA and RB are both in input mode. When RA and RB are used as output ports,
CMOS or NMOS open drain output type can be selected by the PM0 register. Each pin of port RA or
RB can be specified as input or output mode independently by the PM1 and PM2 registers. The MOVA
R, RA or MOVA R, RB instructions operate the input functions and the MOV RA, R or MOV RB, R
operate the output functions. For more details, refer to the instruction table and Figure 8.
I/O PIN
RA.n(RB.n)
DATA
BUS
Buffer
Output
PM0.0 (or PM0.1)
PM1.n
(or PM2.n)
MOVA R, RA
(or MOVA R, RB)
instruction
MOV RA, R
(or MOV RB, R)
Instruction
Enable
Enable
Vdd
Input/Output Pin of the RA(RB)
Figure 8. Architecture of Input/Output Pins
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