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參數資料
型號: W83877TF
廠商: WINBOND ELECTRONICS CORP
元件分類: 外設及接口
英文描述: Multi-Function I/O Port Controller(用于個人計算機的多功能輸入/輸出口控制器)
中文描述: MULTIFUNCTION PERIPHERAL, PQFP100
封裝: QFP-100
文件頁數: 135/154頁
文件大小: 821K
代理商: W83877TF
W83877TF
Publication Release Date: March 1998
- 109 -
Version 0.61
8.2.48 Configuration Register 41 (CR41), default=00H
When the device is in Extended Function mode and EFIR is 41H, the CR41 register can be accessed
through EFDR. The bit definitions are as follows:
1
2
3
4
5
6
7
0
URBTRAPSTS
URATRAPSTS
FDCTRAPSTS
PRTTRAPSTS
reserved
reserved
reserved
reserved
Bit 7 - bit 4 : Reserved, fixed at 0.
Bit 3 - bit 0 : Devices' trap status.
These bits indicate that the individual device wakes up due to any I/O access, IRQ, and external input
to the device respectively. The device's idle timer reloads the initial count value from CR35-CR39,
depending on which device wakes up. These 4 bits are controlled by the printer port, FDC, UART A,
and UART B power down machines individually. The bits are set/cleared by W83877TF
automatically. Writing a 1 can also clear this bit, and writing a 0 has no effect.
PRTTRAPSTS (Bit 3): printer port trap status.
0
the printer port is now in the sleeping state.
1
the printer port is now in the working state due to any printer port access, any
IRQ, any DMA acknowledge, and any transition on BUSY,
ACK
, PE, SLCT, and
ERR
pins.
FDCTRAPSTS (Bit 2): FDC trap status.
0
1
FDC is now in the sleeping state.
FDC is now in the working state due to any FDC access, any IRQ, any DMA
acknowledge, and any enabling of the motor enable bits in the DOR register.
URATRAPSTS (Bit 1): UART A trap status.
0
UART A is now in the sleeping state.
1
UART A is now in the working state due to any UART A access, any IRQ, the
receiver begins receiving a start bit, the transmitter shift register begins
transmitting a start bit, and any transition on MODEM control input lines.
URBTRAPSTS (Bit 0): UART B trap status.
0
UART B is now in the sleeping state.
1
UART B is now in the working state due to any UART B access, any IRQ, the
receiver begins receiving a start bit, the transmitter shift register begins
transmitting a start bit, and any transition on MODEM control input lines.
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參數描述
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