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參數(shù)資料
| 型號(hào)： | W83877TF |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Multi-Function I/O Port Controller(用于個(gè)人計(jì)算機(jī)的多功能輸入/輸出口控制器) |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP100 |
| 封裝： | QFP-100 |
| 文件頁數(shù)： | 141/154頁 |
| 文件大小： | 821K |
| 代理商： | W83877TF |
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W83877TF
Publication Release Date: March 1998
- 115 -
Version 0.61
For the bus master to raise an event to the ACPI software, BM_CNTRL, BM_RLD, and BM_STS bits
are involved. Both BM_RLD and BM_STS are controlled by the ACPI software. If BM_CNTRL is set
by the BIOS software and BM_RLD is set by the ACPI software, an SCI interrupt is raised. Writing a
1 to BM_CNTRL sets it to logic 1 and also sets BM_STS to logic 1; Writing a 0 to BM_CNTRL has no
effect. Writing a 1 to BM_STS clears it to logic 0 and also clears BM_CNTRL to logic 0; writing a 0 to
BM_STS has no effect.
8.3.2 Power Management Timer
In the ACPI specification, it requires a power management timer. The power management timer is a
24-bit fixed rate free running count-up timer that runs off a 3.579545MHZ clock. The power
management timer has the corresponding status bit (TMR_STS) and enable bit (TMR_EN). The
TMR_STS bit is set any time the last bit of the timer (bit 23) goes from 0 to 1 or from 1 to 0. If the
TMR_EN bit is set, the setting of the TMR_STS bit will generate an SCI interrupt. Three registers are
used to read the timer value, they are located in the PM1 register block. The power management
timer has one enable bit (TMR_ON) to turn if on or off. The TMR_ON is located in GPE register
block. If it is cleared to 0, the power management timer function would not work. There are no timer
reset requirements, except that the timer should function after power-up. See the following figure for
illustration.
To SCI Logic
24 bit
counter
Bits (23-0)
TMR_STS
TMR_EN
TMR_ON
3.579545 MHz
24
TMR_VAL
8.4 ACPI Registers (ACPIRs)
The ACPI register model consists of the fixed register blocks that perform the ACPI functions. A
register block may be a event register block which deals with ACPI events or a control register block
which deals with control features. The ordering in the event register block is the status register,
followed by the enable register.
Each event register, if implemented, contains two two register: a status register and an enable
register, both in 16-bit size. The status register indicates what defined function needs the ACPI
System Control Interrupt (SCI). While the hardware event occurs, the defined status bit is set.
However, to generate the SCI, the associated enable bit is required to be set. If the enable bit is not
set, the software can examine the state of the hardware event by reading the status bit without
generating an SCI interrupt.
Any status bit, unless otherwise noted, can only be set by some defined hardware event. It is cleared
by writing a 1 to its bit position and writing a 0 has no effect. Except for some special status bits,
every status bit has an associated enable bit in the same bit position in the enable register. Those
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| W83877TG | 功能描述:IC I/O CONTROLLER 100-PQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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