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參數資料
| 型號： | W742C81A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT MICROCONTROLLER |
| 中文描述： | 4-BIT, FLASH, MICROCONTROLLER, UUC100 |
| 封裝： | DIE-100 |
| 文件頁數： | 12/45頁 |
| 文件大小： | 567K |
| 代理商： | W742C81A |
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Preliminary W742E81A/W742C81A
- 12 -
XIN1
XOUT1
Crystal
3.58 MHz
or
400 KHz
XIN1
XOUT1
or
Figure 6-3 System Clock Oscillator Configuration
6.8 Sub-Oscillator
The sub-oscillator is used in dual-clock operation mode. In the sub-oscillator application, just only the
32768 Hz crystal could be connected to XIN2 and XOUT2, and it would not be oscillated in STOP
mode.
6.9 Dividers
Each divider is organized as a 14-bit binary up-counter designed to generate periodic interrupts.
When the main oscillator starts action, the Divider0 is incremented by each clock (F
OSC
). When an
overflow occurs, the Divider0 event flag is set to 1 (EVF.0 = 1). Then, if the Divider0 interrupt enable
flag has been set (IEF.0 = 1), the interrupt is executed, while if the hold release enable flag has been
set (HEF.0 = 1), the hold state is terminated. And the last 4-stage of the Divider0 can be reset by
executing CLR DIVR0 instruction.
If the sub-oscillator starts action, the Divider1 is incremented by each clock (Fs in dual-clock mode or
Fosc/128 in single-clock mode). When an overflow occurs, the Divider1 event flag is set to 1 (EVF.4
= 1). Then, if the Divider1 interrupt enable flag has been set (IEF.4 = 1), the interrupt is executed,
while if the hold release enable flag has been set (HEF.4 = 1), the hold state is terminated. And the
last 4-stage of the Divider1 can be reset by executing CLR DIVR1 instruction. Same as EVF.0, the
EVF.4 is set to 1 periodically. But there are two period time (125 mS & 500mS) that can be selected
by setting the SCR.3 bit. When SCR.3 = 0 (default), the 500 mS period time is selected; SCR.3 = 1,
the 125 mS period time is selected.
6.10 Dual-clock operation
This operation mode is selected by option code. In the dual-clock mode, the clock source of the LCD
frequency selector should be the sub-oscillator clock (32768 Hz) only. But in the signal-clock mode,
the clock source of the LCD frequency selector will be Fm/128(Fm : main oscillator clock, See figure
6-4).
So before the STOP instruction is executing, the LCD must be turned off in the signal-
clock mode or dual-clock mode
.
In this dual-clock mode, the normal operation is performed by generating the system clock from the
main-oscillator clock (Fm). As required, the slow operation can be performed by generating the
system clock from the sub-oscillator clock (Fs). The exchange of the normal operation and the slow
operation is performed by resetting or setting the bit 0 of the System clock Control Register (SCR). If
the SCR.0 is reset to 0, the clock source of the system clock generator is main-oscillator clock; if the
SCR.0 is set to 1, the clock source of the system clock generator is sub-oscillator clock. In the dual-
clock mode, the main-oscillator can stop oscillating when the STOP instruction is executing or the
SCR.1 is set to 1.
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相關代理商/技術參數 |
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| W742CE811 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:4-BIT MICROCONTROLLER |
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