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參數資料
| 型號： | W742C81A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT MICROCONTROLLER |
| 中文描述： | 4-BIT, FLASH, MICROCONTROLLER, UUC100 |
| 封裝： | DIE-100 |
| 文件頁數： | 19/45頁 |
| 文件大小： | 567K |
| 代理商： | W742C81A |
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Preliminary W742E81A/W742C81A
Publication Release Date: April 2000
Revision A1
- 19 -
6.12.4 Mode Register 1 (MR1) & MFP Control Pin (BUZCR)
Mode Register 1 is organized as a 4-bit binary register (MR1.0 to MR1.3). MR1 can be used to control
the operation of Timer 1. The bit descriptions are as follows:
W
W
W
W
0
1
2
3
MR1
Note: W means write only.
Bit 0 = 0 The internal fundamental frequency of Timer 1 is F
OSC
.
= 1 The internal fundamental frequency of Timer 1 is F
OSC
/64.
Bit 1 = 0 The fundamental frequency source of Timer 1 is the internal clock.
= 1 The fundamental frequency source of Timer 1 is the sub-oscillator frequency Fs (32768
Hz).
Bit 2 is reserved.
Bit 3 = 0 Timer 1 stops down-counting.
= 1 Timer 1 starts down-counting.
MFP control pin is organized as a 4-bit binary register.
3
W
0
1
2
BUZCR
Note: W means write only.
Bit 0 = 0 The specified waveform of the MFP generator is delivered to the MFP output pin.
= 1 The specified frequency of Timer 1 is delivered to the MFP output pin.
Bit 1, Bit 2 & Bit 3 are reserved.
6.13 Interrupts
The W742E81A/W742C81A provides four internal interrupt sources (Divider 0, Divider 1, Timer 0,
Timer 1) and one external interrupt source (port RC). Vector addresses for each of the interrupts are
located in the range of program memory (ROM) addresses 004H to 020H. The flags IEF, PEF, and
EVF are used to control the interrupts. When EVF is set to "1" by hardware and the corresponding bits
of IEF and PEF have been set by software, an interrupt is generated. When an interrupt occurs, all of
the interrupts are inhibited until the EN INT or MOV IEF,#I instruction is invoked. The interrupts can
also be disabled by executing the DIS INT instruction. When an interrupt is generated in hold mode,
the hold mode will be released momentarily and interrupt subroutine will be executed. After the RTN
instruction is executed in an interrupt subroutine, the
μ
C will enter hold mode again. The operation
flow chart is shown in Figure 6-9. The control diagram is shown in Figure 6-9.
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